On the second access (the access of word 120), in which index will the block containing 120 be placed?
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- A two-level cache hierarchy of L1 and L2 with 2 and 3 blocks respectively is designed. Both L1 and L2 are fully-associative with LRU replacement policy. A sequence of references (block addresses from left to right, denoted as letters) is given in the table. Both caches are empty initially. You need to simulate the contents of L1 and L2 for the given sequence. Note that each request goes to L1 first. A request is issued to L2 only if it misses L1. In case of a L2 hit, the requested block is fetched from L2 and placed into L1, both in the MRU position. In case of a L2 miss, the block is loaded from memory into both L1 and L2 caches in the MRU position. The cache contents are displayed by the block addresses from MRU position to LRU position, separated by a comma.For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache.Tag Index Offset31–10 9–5 4–01. What is the cache block size (in words)?2. How many entries does the cache have?3. What is the ratio between total bits required for such a cache implementation over the data storage bits?Starting from power on, the following byte-addressed cache references are recorded. Address 0 4 16 132 232 160 1024 30 140 3100 180 2180 How many blocks are replaced? What is the hit ratio? List the fi nal state of the cache, with each valid entry represented as a record of <index, tag, data>Consider a fully-associative cache of size 4. Each slot in the cache can have just one item (i.e. the line size is 1 item). The cache is empty to start with. The cache uses an LRU replacement policy: every slot has a counter; every time a slot is accessed, a global counter is incremented and the value is stored in the slot counter; the slot with the lowest counter value is chosen for replacement. Sequence Id 1 2 3 4 5 6 7 8 10 Address Ox0012 0x0014 Ox0016 Ox0018 0x0016 0x0012 0x0020 Ox0022 0x0014 Ox0012 Hit/Miss Accesses 1 to 10 are respectively: Select one: O a. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Miss, Miss O b. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Hit, Hit O. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Hit, Miss O d. Miss, Miss, Miss, Miss, Hit, Miss, Miss, Miss, Miss, Hit O e. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Miss, Hit
- We are given a list of 64-bit memory address references, given as word addresses. Ox03, Oxb4, Ox2b, 0x02, Oxbf, Ox58, Oxbe, OxOe, Oxb5, Ox2c, Oxba, Oxfd (A) For each of these references, identify the binary word address, the tag, and the index given a direct-mapped cache with 16 one-word blocks. Also list whether each reference is a hit or a miss, assuming the cache is initially empty. (B) For each of these references, identify the binary word address, the tag, the index, and the offset given a direct-mapped cache with two- word blocks and a total size of eight blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. (C) You are asked to optimize a cache design for the given references (i.e. addresses). There are three direct-mapped cache designs possible, all with a total of eight words of data: (i) Cache1 has 1-word blocks, (ii) Cache2 has 2-word blocks, and (iii) Cache3 has 4-word blocks.For the cache design of the preceding problem, suppose that increasing the line size from one word to four words results in a decrease of the read miss rate from 3.2% to 1.1%. For both the nonburst transfer and the burst transfer case, what is the average miss penalty, averaged over all reads, for the two different line sizes?Give an example where higher set associativity really raises miss rate in the miss rate table. To show this, build a cache setup and a reference stream.
- Using the references from Exercise 5.2, show the final cache contents for a fully associative cache with one-word blocks and a total size of 8 words. Use LRU replacement. For each reference identify the index bits, the tag bits, and if it is a hit or a miss.For a direct-mapped cache design with a 32-bit address, the following bits ofthe address are used to access the cache. We assume that each word has 4 bytes. Hints:this is a multiword block direct-mapped cache because each cache block (i.e., each cacheline or each cache entry) contains multiple words. The width of the “Byte offset” segmentis 2 (i.e., the lowest two bits of a 32-bit address), which indicates that each word has 4bytes. The width of the “Block offset” segment (i.e., from the 2nd bit to the 5th bit of a 32-bit address) determines the number of words per cache line. A) What is the cache line size (in words)? B) How many entries does the cache have? C) What is the ratio between total bits required for such a cacheimplementation over the data storage bits?Now, we consider a 16-byte, four-way, fully- associative cache. Since the capacity of the cache is 16 bytes, the array "a" in our example (does/does not) fit inside the cache. We can deduce that the block size for this cache is (? ) bytes per block. So the block index size b=2 bits. For a memory trace record such as: L 1fff000116,2 the 2-bit block offset is (Ob01/0b10/0bl1/0b00). The tag bits are all the rest of the bits not part of the block offset.
- Now, we consider a 16-byte, four-way, fully-associative cache. Since the capacity of the cache is 16 bytes, the array "a" in our example (does/does not) fit inside the cache. We can deduce that the block size for this cache is ( ? ) bytes per block. So the block index size b=2 bits. For a memory trace record such as: L 1fff000116,2 the 2-bit block offset is (0b01/0b10/0b11/0b00). The tag bits are all the rest of the bits not part of the block offset.Different algorithms are used for scheduling the disk head so that seek time may be reduced. Calculate total number of heads movement for the following algorithms for the given disk queue with requests for I/O to blocks on cylinders in that order. Queue = 98, 183, 37, 122, 14, 124, 65, 67 If the disk head is initially at cylinder 53 and direction is Right. FCFS – First-Come, First-Served - FCFSFor a physically Indexed L1D cache, what is the average read latency if TLB hit rate is 99.5% and the L1 data cache hit rate is 98%? Assume TLB hit latency: 0.5 nS, L1D hit latency: 1ns, L2 hit latency: 10nS. Assume L2 hit rate is 100% and page tables are cached.