Number 9: module Decoder (w0, w1, w2, En, y0, y1, y2, y3, y4, y5, y6, y7); input w0, w1, w2, En; output y0, y1, y2, y3, y4, y5, y6, y7; assign yo = W0 & w1 & w2 & En; assign y1 = ~w0 & -w1 & w2 & En; assign y2 = ~w0 & w1 & -w2 & En; assign y3 = ~w0 & w1 & w2 & En; assign y4=w0 & ~w1 & ~w2 & En; assign y5 = w0 & -w1 & w2 & En; assign y6 = w0 & w1 & -w2 & En; assign y7= w0 & w1 & w2 & En; endmodule

COMPREHENSIVE MICROSOFT OFFICE 365 EXCE
1st Edition
ISBN:9780357392676
Author:FREUND, Steven
Publisher:FREUND, Steven
Chapter5: Working With Multiple Worksheets And Workbooks
Section: Chapter Questions
Problem 7AYK
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Using the given Verilog code, please convert to a STRUCTURAL verilog code with the given truth table and verilog code in the images . I have added the truth table and verilog code for reference. I JUST NEED IT TO BE CONVERTED INTO STRUCTURAL
пomework 2 #q
W₁ W₂ Yo
Yo Y₁
En Wo W₁ W₂
ох хх
оо
110 00 I о
О
I
о о
оо
0
О
1001
|10 10
10
|
|
| |
оо
0 1
(то
| | | |
О
о о
о о
Үг Ўз Yи Үд чи
ооо
ово
ооо
ооо
ооо
о о
о о
I о
О
о
О
о
О
о
о о
оооо
о
Ут
оооо
1000
тоо
о
01 о
1
Transcribed Image Text:пomework 2 #q W₁ W₂ Yo Yo Y₁ En Wo W₁ W₂ ох хх оо 110 00 I о О I о о оо 0 О 1001 |10 10 10 | | | | оо 0 1 (то | | | | О о о о о Үг Ўз Yи Үд чи ооо ово ооо ооо ооо о о о о I о О о О о О о о о оооо о Ут оооо 1000 тоо о 01 о 1
Number 9: module Decoder (w0, w1, w2, En, y0, y1, y2, y3, y4, y5, y6, y7);
input w0, w1, w2, En;
output y0, y1, y2, y3, y4, y5, y6, y7;
assign y0 = w0 & w1 & w2 & En;
assign y1 = ~wO & -w1 & w2 & En;
assign y2 = ~w0 & w1 & ~w2 & En;
assign y3 = ~w0 & w1 & w2 & En;
assign y4 = w0 & ~w1 & ~w2 & En;
assign y5 = w0 & -w1 & w2 & En;
assign y6 = w0 & w1 & ~w2 & En;
assign y7 = w0 & w1 & w2 & En;
endmodule
Transcribed Image Text:Number 9: module Decoder (w0, w1, w2, En, y0, y1, y2, y3, y4, y5, y6, y7); input w0, w1, w2, En; output y0, y1, y2, y3, y4, y5, y6, y7; assign y0 = w0 & w1 & w2 & En; assign y1 = ~wO & -w1 & w2 & En; assign y2 = ~w0 & w1 & ~w2 & En; assign y3 = ~w0 & w1 & w2 & En; assign y4 = w0 & ~w1 & ~w2 & En; assign y5 = w0 & -w1 & w2 & En; assign y6 = w0 & w1 & ~w2 & En; assign y7 = w0 & w1 & w2 & En; endmodule
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