module full_adder(input a, input b, input cin, output sum, output cout); wire s1, c1, c2; xor(sum, a, b); and(c1, a, b); and(c2, sum, cin); or(cout, c1, c2); endmodule module fulladd16_gate(input [15:0] a, input [15:0] b, input cin, output [16:0] sum, output reg cout); wire [15:0] carry; full_adder fa0(a[0], b[0], cin, sum[0], carry[0]); full_adder fa1(a[1], b[1], carry[0], sum[1], carry[1]); full_adder fa2(a[2], b[2], carry[1], sum[2], carry[2]); full_adder fa3(a[3], b[3], carry[2], sum[3], carry[3]); full_adder fa4(a[4], b[4], carry[3], sum[4], carry[4]); full_adder fa5(a[5], b[5], carry[4], sum[5], carry[5]); full_adder fa6(a[6], b[6], carry[5], sum[6], carry[6]); full_adder fa7(a[7], b[7], carry[6], sum[7], carry[7]); full_adder fa8(a[8], b[8], carry[7], sum[8], carry[8]); full_adder fa9(a[9], b[9], carry[8], sum[9], carry[9]); full_adder fa10(a[10], b[10], carry[9], sum[10], carry[10]); full_adder fa11(a[11], b[11], carry[10], sum[11], carry[11]); full_adder fa12(a[12], b[12], carry[11], sum[12], carry[12]); full_adder fa13(a[13], b[13], carry[12], sum[13], carry[13]); full_adder fa14(a[14], b[14], carry[13], sum[14], carry[14]); full_adder fa15(a[15], b[15], carry[14], sum[15], carry[15]); assign sum[16] = carry[15]; endmodule This is my 16-bit adder module. and module stimulus; wire [17-1:0] sum; reg [16-1:0] a, b; reg [17-1:0] mat_sum; reg [16-1:0] mat_a_input [0:99]; reg [16-1:0] mat_b_input [0:99]; reg [17-1:0] mat_sum_output [0:99]; fulladd16_gate gate1(.a(a), .b(b), .cin(1'b0), .sum(sum)); integer i; integer err; initial begin $readmemh("a_input.txt", mat_a_input); $readmemh("b_input.txt", mat_b_input); $readmemh("sum_output.txt", mat_sum_output); i=0; err = 0; #10; for (i=0; i<100; i = i+1) begin a = mat_a_input[i]; b = mat_b_input[i]; mat_sum = mat_sum_output[i]; #10; if(sum != mat_sum) err = err + 1; end end endmodule This is my test bench code. I want to make the input and output flip-flop so that the calculation is performed for each negative edge of the clk. Could you tell me the code of the module that added the flip-flop like that and the test bench code to check it?
module full_adder(input a, input b, input cin, output sum, output cout);
wire s1, c1, c2;
xor(sum, a, b);
and(c1, a, b);
and(c2, sum, cin);
or(cout, c1, c2);
endmodule
module fulladd16_gate(input [15:0] a, input [15:0] b, input cin, output [16:0] sum, output reg cout);
wire [15:0] carry;
full_adder fa0(a[0], b[0], cin, sum[0], carry[0]);
full_adder fa1(a[1], b[1], carry[0], sum[1], carry[1]);
full_adder fa2(a[2], b[2], carry[1], sum[2], carry[2]);
full_adder fa3(a[3], b[3], carry[2], sum[3], carry[3]);
full_adder fa4(a[4], b[4], carry[3], sum[4], carry[4]);
full_adder fa5(a[5], b[5], carry[4], sum[5], carry[5]);
full_adder fa6(a[6], b[6], carry[5], sum[6], carry[6]);
full_adder fa7(a[7], b[7], carry[6], sum[7], carry[7]);
full_adder fa8(a[8], b[8], carry[7], sum[8], carry[8]);
full_adder fa9(a[9], b[9], carry[8], sum[9], carry[9]);
full_adder fa10(a[10], b[10], carry[9], sum[10], carry[10]);
full_adder fa11(a[11], b[11], carry[10], sum[11], carry[11]);
full_adder fa12(a[12], b[12], carry[11], sum[12], carry[12]);
full_adder fa13(a[13], b[13], carry[12], sum[13], carry[13]);
full_adder fa14(a[14], b[14], carry[13], sum[14], carry[14]);
full_adder fa15(a[15], b[15], carry[14], sum[15], carry[15]);
assign sum[16] = carry[15];
endmodule
This is my 16-bit adder module. and
module stimulus;
wire [17-1:0] sum;
reg [16-1:0] a, b;
reg [17-1:0] mat_sum;
reg [16-1:0] mat_a_input [0:99];
reg [16-1:0] mat_b_input [0:99];
reg [17-1:0] mat_sum_output [0:99];
fulladd16_gate gate1(.a(a), .b(b), .cin(1'b0), .sum(sum));
integer i;
integer err;
initial
begin
$readmemh("a_input.txt", mat_a_input);
$readmemh("b_input.txt", mat_b_input);
$readmemh("sum_output.txt", mat_sum_output);
i=0;
err = 0;
#10;
for (i=0; i<100; i = i+1)
begin
a = mat_a_input[i];
b = mat_b_input[i];
mat_sum = mat_sum_output[i];
#10;
if(sum != mat_sum)
err = err + 1;
end
end
endmodule
This is my test bench code. I want to make the input and output flip-flop so that the calculation is performed for each negative edge of the clk. Could you tell me the code of the module that added the flip-flop like that and the test bench code to check it?
Step by step
Solved in 4 steps
