Memory Performance: The following questions will refer to the same instruction mix as above, with the following additional information: Processor P1: 42% of all instructions are memory access instructions. Level 1 Cache Access=0.68 ns Main Memory Access - 59 ns 12% of all memory access is a "miss". 9. The clock rate of the processor = 10 The Average Memory Access Time for the given data- GHz. ns _cycles 11. The Average number of cycles for a memory access = 12. Assuming that the base CPI = 1.0 cycles, and using the answer from #11, the average time to complete an instruction for the program described ns 8
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- AsapA microprocessor has a 32-bit address line. The size of the memory contents of each address is 8 bits. The memory space is defined as the collection of memory position the processor can address. What is the address range (lowest to highest, in hexadecimal) of the memory space for this microprocessor? What is the size (in bytes, KB, or MB) of the memory space? 1 KB = 21010 bytes, 1MB = 22020 bytes, 1GB = 23030 bytes A memory device is connected to the microprocessor. Base o the size of the memory, the microprocessor has assigned the addresses 0xA4000000 to 0xA07FFFFF to this memory device. What is the size (in bytes, KB, or MB) of this memory device? What is the minimum number of bits required to represent the addresses only for this memory device?Suppose cache has a hit rate of 0.89 and access time of 5ns, main memory has a hit rate of 0.98 and access time of 60ns, and virtual memory has an access time of 700 us (microseconds). What is the average memory access time in us?
- A memory hierarchy contains a single cache with a miss rate of 2% that holds both instructions and data. The miss penalty to access main memory is 100 cycles. 15% of the instructions are jumps, 20% are stores, 20% are loads (30% have values used in the next instruction), 10% are branches (taken 20% of the time), and 35% are ALU instructions. Jumps and branches are determined in the ID stage. What is the base CPI, and what is the effective CPI?A computer has instructions that require two bus cycles, one to fetch the instruction and one to fetch the data. Each bus cycle takes 250 nanoseconds and each instruction takes 500 nanoseconds (i.e., the internal processing time is negligible). The computer also has a disk with 16,512 byte sectors per track. Disk rotation time is 8.092 milliseconds. To what percentage of its normal speed is the computer reduced during DMA transfer if each DMA takes one bus cycle? Consider two cases: 8-bit bus transfer and 16-bit bus transfer.The memory access time is 1 nanosecond for a read operation with a hit in cache, 5 nanoseconds for a read operation with a miss in cache, 2 nanoseconds for a write operation with a hit in cache and 10 nanoseconds for a write operation with a miss in cache. Execution of a sequence of instructions involves 100 instruction fetch operations, 60 memory operand read operations and 40 memory operand write operations. The cache hit-ratio is 0.9. The average memory access time (in nanoseconds) in executing the sequence of instructions will be ?
- Suppose the cache access time is 10ns, main memory access time is 200ns, and the cache hit rate is 95%. Assuming parallel (overlapped) access (or say, load-through is used), what is the average access time for the processor to access an item?A virtual memory has a page size of 16 words. There are 8 pages and 4 blocks. The associative memory page table contains the following entries. (Addresses are given HEX form): Page Block a) For the following virtual addresses find the CPU addresses: 3A, 5B, 1 3 b) For the following CPU addresses find the virtual addresses: 0C, 2D 1 4Suppose the cache access time is 6ns, main memory access time is 140ns, and the cache hit rate is 85%. Assuming parallel (overlapped) access, what is the average access time for the processor to access an item?
- Using data set E, answer the questions given below. DATA SET E Microprocessor Speed (MHz) and Power Dissipation (watts) (n = 14 chips) Chip Speed (MHz) Power (watts) 1989 Intel 80486 20 3 1993 Pentium 100 10 1997 Pentium II 233 35 1998 Intel Celeron 300 20 1999 Pentium III 600 42 1999 AMD Athlon 600 50 2000 Pentium 4 1300 51 2004 Celeron D 2100 73 2004 Pentium 4 3800 115 2005 Pentium D 3200 130 2007 AMD Phenom 2300 95 2008 Intel Core 2 3200 136 2009 Intel Core i7 2900 95 2009 AMD Phenom II 3200 125 (a)Obtain the regression equation. (Round your answers to 3 decimal places.) (b) Calculate R2. (Round your answer to 3 decimal places.)A computer system has an L1 cache, an L2 cache, and a main memory unit 10.4k view= connected as shown below. The block size in L1 cache is 4 words. The block size in L2 cache is 16 words. The memory access times are 2 nanoseconds, 20 nanoseconds and 200 nanoseconds for L1 cache, L2 cache and the main memory unit respectively. Data Data Bus Bus L1 L2 Main Cache Cache Memory 4 words 4 words When there is a miss in both L1 cache and L2 cache, first a block is transferred from main memory to L2 cache, and then a block is transferred from L2 cache to L1 cache. What is the total time taken for these transfers?A program sees a 4% miss rate on both the Instruction Cache and the Data Cache. Every instruction requires access to the Instruction cache. Only 35% of the instructions require data access from the Data Cache. The miss penalty for either the data or the instruction cache is 100 cycles. Assume the average Clocks per Instruction (CPI) is 2 without any memory stalls (this is a hypothetical machine where if there were no misses on that instruction, it would get executed in 2 clock cycles. We are not worrying about how it is implemented, just, that suppose it was possible). Assume the number of instructions in a program is X. F1: What is the number of 'instruction miss cycles'? (The number of clock cycles lost due to a miss on the Instruction Cache) F2: What is the number of 'data miss cycles'? F3: What is the total run time of the program including the missed cycles dues to data and instruction misses? F4: What is the ratio of the actual run time (from question F3 above) to the…