Main Memory Management worst fit: given the initial status of the partition table is as the following, after processes A(15M), B(12M), C(5M) and D(7M) are loaded to the main memory one by another, what the partition table will be? dynamic-partition no. 1 2 3 4 available size 20 15 10 2 starting physical address 10 40 30 status 0 0 0 0

Main Memory Management worst fit: given the initial status of the partition table is as the following, after processes A(15M), B(12M), C(5M) and D(7M) are loaded to the main memory one by another, what the partition table will be? dynamic-partition no. 1 2 3 4 available size 20 15 10 2 starting physical address 10 40 30 status 0 0 0 0

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter11: Operating Systems

Section: Chapter Questions

Problem 21VE

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Main memory size is 16 pages. Size of swap file on hard disk is 64 pages. Operating system locks down pages 0, 1, 2 and 7 in the main memory. Two programs are started and both are provided with a virtual address space of 10 pages. Initially operating system allocates 5 pages of main memory for each program and the rest from swap file. Virtual address space of each program starts from page 0. Construct page tables for both programs at program startup. A page table consists of P-bit which tells if the page is present in the main memory (1 = page is in main memory) and address of the page. Address tells either real address in main memory or the address of the page in swap file. b. A computer with a paged virtual memory system executes two load instructions that are adjacent to each other in memory. Describe the worst case scenario (in terms of performance) that can occur during the execution of the two instructions and explain under which conditions this case occurs. How does this affect…
In the S/370 architecture, a storage key is a control field associated with each page- sized frame of real memory. Two bits of that key that are relevant for page replace- ment are the reference bit and the change bit. The reference bit is set to 1 when any address within the frame is accessed for read or write, and is set to 0 when a new page is loaded into the frame. The change bit is set to 1 when a write operation is per- formed on any location within the frame. Suggest an approach for determining which page frames are least-recently-used, making use of only the reference bit.
The principal advantage is a savings in physical memory space. This occurs for two reasons: (1) a user page table can be paged in to memory only when it is needed. (2) The operating system can allocate user page tables dynamically, creating one only when the process is created. Of course, there is a disadvantage: address translation requires extra work.
Answer the following short questions to the point. Which bit in the PTE does the operating system use for approximating LRU replacement? Does a TLB miss always/sometimes/never result in a paging from disk? What are the two components of a virtual address used in segmented virtual memory? In what Nachos file was StartProcess implemented? What kind of pages in a process’ virtual address space are usually protected as “Read Only”? Is it possible to implement a file system inside of a file stored in another file system?
Consider a file system that uses inodes to represent files. Disk blocks are 16 KB in size, and a pointer to a disk block requires 4 bytes. This file system has 12 direct disk blocks, as well as single, double, and triple indirect disk blocks. What is the maximum size of a file that can be stored in this file system? Show calculation steps
Given: physical memory size: 290k Assume the OS occupies the first 40k. Simulate using multiple partition allocation (MVT) What is the size of the hole at time 7? What is the size of the hole at time 19? What is the starting address of process T3 in the memory? What is the starting address of process T4 in the memory? What is the starting address of process T5 in the memory? At what time will all the processes be terminated?
In the event that a request cannot be fulfilled by the cache, the processor will submit a request to main memory while the write buffer delivers the relevant data block. What steps need to be taken here?
It is possible to lessen the latency of accesses between various levels of the memory hierarchy by using buffers. For the above configuration, can you list any conceivable buffers between the L1 and L2 caches, as well as between the L2 cache and the RAM?
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Given the initial partition table as followings and processes A(8M), B(6M), C(12M), D(1M) loaded to the memory one by another
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Which bit in the PTE does the operating system use for approximating LRU replacement? Does a TLB miss always/sometimes/never result in a paging from disk? What are the two components of a virtual address used in segmented virtual memory? In what Nachos file was StartProcess implemented? What kind of pages in a process’ virtual address space are usually protected as “Read Only”? Is it possible to implement a file system inside of a file stored in another file system?