lw $s1, 24($t3) add $t2, $s1, $t1 In the standard five stage, pipelined machine, consider the above two instructions where the second instruction tries to read a register that is being written to by the first instruction which is a 'load word' (lw) command. The scheduler has not done any juxtaposing of the commands. a. There will be no hazard situation as the load word deals with the data memory and the read is from the registers. b. There will be no hazard situation, since the read is from the same location where the write is taking place. c. It is possible to avoid a bubble in the flow by forwarding from the write back stage.
lw $s1, 24($t3) add $t2, $s1, $t1 In the standard five stage, pipelined machine, consider the above two instructions where the second instruction tries to read a register that is being written to by the first instruction which is a 'load word' (lw) command. The scheduler has not done any juxtaposing of the commands. a. There will be no hazard situation as the load word deals with the data memory and the read is from the registers. b. There will be no hazard situation, since the read is from the same location where the write is taking place. c. It is possible to avoid a bubble in the flow by forwarding from the write back stage.
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
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Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Consider the two back to back instructions:
lw $s1, 24($t3)
add $t2, $s1, $t1
In the standard five stage, pipelined machine, consider the above two instructions where the second instruction tries to read a register that is being written to by the first instruction which is a 'load word' (lw) command. The scheduler has not done any juxtaposing of the commands.
a. There will be no hazard situation as the load word deals with the data memory and the read is from the registers.
b. There will be no hazard situation, since the read is from the same location where the write is taking place.
c. It is possible to avoid a bubble in the flow by forwarding from the write back stage.
d. It is not possible to avoid Data Hazard issues here and inserting a bubble is a way out of this issue.
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