Laboratory Exercise 1 | Numbers and Displays This is an exercise in designing combinational circuits that can perform binary-to-decimal number conversion and binary-coded-decimal (BCD) addition, using Proteus Design Suite. Part I Figure 1a shows a sum-of-products circuit that implements a 2-to-1 multiplexer with a select input s. Ifs=0 the multiplexer's output m is equal to the input x, and if s = 1 the output is equal to y. Figure 1b gives a truth table for this multiplexer, and part c shows its circuit symbol. a) Circuit X3 V3 V x₂ 3/₂ xo Yo m You are to use four instances of the circuit shown above to create the circuit given in Figure 2a. This circuit has two four-bit inputs, X and Y, and produces the four-bit output M. If s = 0 then M = X, while if s = 1 then M = Y. We refer to this circuit as a four-bit wide 2-to-1 multiplexer. It has the circuit symbol shown in Figure 2b, in which X, Y, and M are depicted as four-bit wires. m3 Comparator 9 Circuit A m₂ S Figure 1: A 2-to-1 multiplexer mo 0 1 A m b) Truth table a) Circuit b) Symbol Figure 2: A four-bit wide 2-to-1 multiplexer X y Y Part II into its two-digit You are to design a circuit that converts a four-bit binary number V = v3V2V1V0 decimal equivalent D - dido. Table 1 shows the required output values. A partial design of this circuit is given in Figure 3. It includes a comparator that checks when the value of V is greater than 9 and uses the output of this comparator in the control of the 7-segment displays. You are to complete the design of this circuit. 4 V3V2V1V0 d₁ do 0 0 0000 0001 0 1 0010 0 2 Table 1: Binary-to-decimal conversion values. 1001 0 9 1010 1 0 1011 1 1 1100 1 2 1 3 1101 1110 1 4 1111 1 5 The output z for the comparator circuit can be specified using a single Boolean expression, with the four inputs V3-0. Design this Boolean expression by making a truth table that shows the values of the inputs V3-0 for which z must be 1. 0 1 c) Symbol M 5 4 0 3 m do 6 3 Figure 3: Partial design of the binary-to-decimal conversion circuit Notice that the circuit Figure 3 includes a 4-bit wide 2-to-1 multiplexer. The purpose of multiplexer is to drive digit do with the value of V when z = 0, and the value of A when z = 1. To design circuit A, consider the following. For the input values V≤ 9, circuit A does not matter, because the multiplexer in Figure 3 just selects V in these cases. But for the input values V > 9, the multiplexer will select A. Thus, A must provide output values that properly implement Table 1 when V > 9. You need to design circuit A so that the input V = 1010 gives an output A = 0000, the input V = 1011 gives the output A = 0001, ..., and the input V = 1111 gives the output A = 0101. Design circuit A by making a truth table with the inputs V3-0 and the outputs A3-0.

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Provide a detailed theory, discussion, and conclusion for the activity in the document below.

Laboratory Exercise 1 | Numbers and Displays
This is an exercise in designing combinational circuits that can perform binary-to-decimal number
conversion and binary-coded-decimal (BCD) addition, using Proteus Design Suite.
Part I
Figure 1a shows a sum-of-products circuit that implements a 2-to-1 multiplexer with a select input s.
Ifs=0 the multiplexer's output is equal to the input x, and if s = 1 the output is equal to y. Figure
1b gives a truth table for this multiplexer, and part c shows its circuit symbol.
a) Circuit
V
X3
Y3
x₂.
2 -
xo
Yo
Cout
You are to use four instances of the circuit shown above to create the circuit given in Figure 2a. This
circuit has two four-bit inputs, X and Y, and produces the four-bit output M. If s = 0 then M = X, while
if s = 1 then M = Y. We refer to this circuit as a four-bit wide 2-to-1 multiplexer. It has the circuit
symbol shown in Figure 2b, in which X, Y, and M are depicted as four-bit wires.
m
Comparator
>9
Circuit A
Sum3
FullAdder3
A
Figure 1: A 2-to-1 multiplexer
B
m3
a) Circuit
b) Symbol
Figure 2: A four-bit wide 2-to-1 multiplexer
Cin
m₂
mo
Part II
You are to design a circuit that converts a four-bit binary number V = √3v2v₁v0 into its two-digit
decimal equivalent D - dido. Table 1 shows the required output values. A partial design of this
circuit is given in Figure 3. It includes a comparator that checks when the value of V is greater than 9
and uses the output of this comparator in the control of the 7-segment displays. You are to complete
the design of this circuit.
C₂
Z
A
1001
1010
1011
S
0
1
1100
1101
1110
1111
b) Truth table
V3V2V1V0 d₁ do
0000 0 0
0001
0
1
0010 0 2
Table 1: Binary-to-decimal conversion values.
The output z for the comparator circuit can be specified using a single Boolean expression, with the
four inputs V3-0. Design this Boolean expression by making a truth table that shows the values of
the inputs V3-0 for which z must be 1.
FullAdder2
Sumz
m
4
X
y
X
Y
1
C₂
1
0 9
0
1
2106345
0
1
Sum
FullAdder₁
Figure 3: Partial design of the binary-to-decimal conversion circuit
Notice that the circuit in Figure 3 includes a 4-bit wide 2-to-1 multiplexer. The purpose of this
multiplexer is to drive digit do with the value of V when z = 0, and the value of A when z = 1. To
design circuit A, consider the following. For the input values V≤ 9, circuit A does not matter,
because the multiplexer in Figure 3 just selects V in these cases. But for the input values V> 9, the
multiplexer will select A. Thus, A must provide output values that properly implement Table 1 when V
> 9. You need to design circuit A so that the input V = 1010 gives an output A = 0000, the input V =
1011 gives the output A = 0001, ..., and the input V = 1111 gives the output A = 0101. Design
circuit A by making a truth table with the inputs V3-0 and the outputs A3-0.
Part III
You are to design a circuit that adds the two BCD digits. The inputs to your circuit are the numbers X
and Y, plus a carry-in, cin. You should use the four-bit ripple-carry adder/subtractor (RCAS4) circuit
in Figure 4 below to produce a four-bit sum and carry-out for the operation X + Y. This result is to be
displayed on 7-segment displays as a two-digit sum S₁So. For a sum equal to zero you would display
S₁S0 = 00, for a sum of one S₁S0 = 01, for nine S₁S0 = 09, for ten S₁S0 = 10, and so on. Note that the
inputs X and Y are assumed to be decimal digits, which means that the largest sum that needs to be
handled by this circuit is S₁S0 = 9 + 9 + 1 = 19.
C₁
G
M
FullAddero
Sumo
0
Figure 4 Schematic diagram 4-bit ripple-carry adder/subtractor (RCAS4)
c) Symbol
Sum
Cout
Figure 5 Circuit diagram for a full adder
4
d₁
0
6
m
0
6
3
1
12
|-|
|~|
|~||
Transcribed Image Text:Laboratory Exercise 1 | Numbers and Displays This is an exercise in designing combinational circuits that can perform binary-to-decimal number conversion and binary-coded-decimal (BCD) addition, using Proteus Design Suite. Part I Figure 1a shows a sum-of-products circuit that implements a 2-to-1 multiplexer with a select input s. Ifs=0 the multiplexer's output is equal to the input x, and if s = 1 the output is equal to y. Figure 1b gives a truth table for this multiplexer, and part c shows its circuit symbol. a) Circuit V X3 Y3 x₂. 2 - xo Yo Cout You are to use four instances of the circuit shown above to create the circuit given in Figure 2a. This circuit has two four-bit inputs, X and Y, and produces the four-bit output M. If s = 0 then M = X, while if s = 1 then M = Y. We refer to this circuit as a four-bit wide 2-to-1 multiplexer. It has the circuit symbol shown in Figure 2b, in which X, Y, and M are depicted as four-bit wires. m Comparator >9 Circuit A Sum3 FullAdder3 A Figure 1: A 2-to-1 multiplexer B m3 a) Circuit b) Symbol Figure 2: A four-bit wide 2-to-1 multiplexer Cin m₂ mo Part II You are to design a circuit that converts a four-bit binary number V = √3v2v₁v0 into its two-digit decimal equivalent D - dido. Table 1 shows the required output values. A partial design of this circuit is given in Figure 3. It includes a comparator that checks when the value of V is greater than 9 and uses the output of this comparator in the control of the 7-segment displays. You are to complete the design of this circuit. C₂ Z A 1001 1010 1011 S 0 1 1100 1101 1110 1111 b) Truth table V3V2V1V0 d₁ do 0000 0 0 0001 0 1 0010 0 2 Table 1: Binary-to-decimal conversion values. The output z for the comparator circuit can be specified using a single Boolean expression, with the four inputs V3-0. Design this Boolean expression by making a truth table that shows the values of the inputs V3-0 for which z must be 1. FullAdder2 Sumz m 4 X y X Y 1 C₂ 1 0 9 0 1 2106345 0 1 Sum FullAdder₁ Figure 3: Partial design of the binary-to-decimal conversion circuit Notice that the circuit in Figure 3 includes a 4-bit wide 2-to-1 multiplexer. The purpose of this multiplexer is to drive digit do with the value of V when z = 0, and the value of A when z = 1. To design circuit A, consider the following. For the input values V≤ 9, circuit A does not matter, because the multiplexer in Figure 3 just selects V in these cases. But for the input values V> 9, the multiplexer will select A. Thus, A must provide output values that properly implement Table 1 when V > 9. You need to design circuit A so that the input V = 1010 gives an output A = 0000, the input V = 1011 gives the output A = 0001, ..., and the input V = 1111 gives the output A = 0101. Design circuit A by making a truth table with the inputs V3-0 and the outputs A3-0. Part III You are to design a circuit that adds the two BCD digits. The inputs to your circuit are the numbers X and Y, plus a carry-in, cin. You should use the four-bit ripple-carry adder/subtractor (RCAS4) circuit in Figure 4 below to produce a four-bit sum and carry-out for the operation X + Y. This result is to be displayed on 7-segment displays as a two-digit sum S₁So. For a sum equal to zero you would display S₁S0 = 00, for a sum of one S₁S0 = 01, for nine S₁S0 = 09, for ten S₁S0 = 10, and so on. Note that the inputs X and Y are assumed to be decimal digits, which means that the largest sum that needs to be handled by this circuit is S₁S0 = 9 + 9 + 1 = 19. C₁ G M FullAddero Sumo 0 Figure 4 Schematic diagram 4-bit ripple-carry adder/subtractor (RCAS4) c) Symbol Sum Cout Figure 5 Circuit diagram for a full adder 4 d₁ 0 6 m 0 6 3 1 12 |-| |~| |~||
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