In the process of testing a 74LS283 4-bit parallel adder, the following logic levels were observed on its pins: (Please check the datasheet of 74LS283 for more details.) Pin number 1 Logic level HIGH 2 HIGH 3 HIGH 4 HIGH 5 LOW 6 LOW 7 LOW 8 LOW 9 HIGH 10 LOW 11 HIGH 12 LOW 13 HIGH 14 HIGH 15 HIGH HIGH 16 Determine if the IC is functioning properly. If not, what should be the correct logic level at each pin. You need to give as much analysis details as possible.
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- Design Mod 70 counter using IC # 74293. You can use other logic gates if necessary.a) Before designing the combinational circuit, you need to identify the pin configuration of the 7-segment diplay chip. Using the data book, write the pin configuration of the two 7- segment diplay chip. Pin # (top) Left to right Pin# (bottom) Left to right 1 2 123 466 7 8 9 3 4 8. el a lo 7 9. 9 1? 345 6 7 8 9Describe the conditions and what happens in a given BCS when data flow directly from the internal programmable logic to a device output pin.
- 3. Complete the timing diagram for the following circuit: ENABLE CLK IN ENABLE IN MUX_OUT For ENABLE = 0, MUX_OUT = IN CLK MUX_OUT SET D Q CLR Q U UQuestion:Given the VHDL code for an 8-bit numbers comparator, draw the schematic of your circuit, showing the inputs and outputs. Here is the VHDL code for an 8-bit numbers comparator: LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_arith.all ;ENTITY Mag_Comp_8Bit ISPORT ( A, B : IN STD_LOGIC_vector(7 DOWNTO 0) ;AeqB, AgtB, AltB : OUT STD_LOGIC ) ;END Mag_Comp_8Bit;ARCHITECTURE Behavior OF Mag_Comp_8Bit ISbeginAgtB<= '1' when (A > B)else '0';AeqB <= '1' when (A = B)else '0';AltB <= '1' when (A < B)else '0';END Behavior ;Design a full subtractor circuit performing A-(B-C) using optimum size and number of multiplexer/s. You may use block diagrams to represent your multiplexer/s. Label your I/O pins properly and completely. Show your complete solution
- Ex4: Design a counter with 7 flip-flops that goes through the following binary repeated sequence: 0, 1, 3, 7, 6, 4. Show that when binary states 010 and 101 are considered as don't care conditions, the counter may not operate properly. Find a way to correct the design with don't care and without don't care The number of flip-flops required is three. • Table below shows the desired circuit excitation table. Present Next Flip-flop inputs state state ABC ABC TA TB C 000 001 0 0 1 001 011 0 1 0 010 XXX X X X 011 111 1 1 0 100 000 1 1 0 101 XXX X X X 110 100 0 1 0 111 110 0 0 1TZTIT -00 Time left: Given in the figure is IC 7474 pin configuration. The pin connections of the IC is provided in the Table for the design of a particular counting sequence. What is that counting sequence for which it is desined. Intially the FFs states (AB) were reset to 10. Dtype Flip-flop Two vcc CUR 1413U12L aK PR THEHOHOHOHOH CLR D CLKPR O GND D-ype Fip-fop One Table PIN NUMBERS Signal Value VCC (Logic 1) Connected with a common clock 1,4, 10, 13 and 14 3 and 11 6. A' 7. Ground (Logic 0) B" B. 2. VCC (Logic 1) Is connected with PIN 8 12 O a. (AB): 10--> 00 --> 10 O b. (AB): 10-->11-> 10 Oc (AB): 10-->11-->01 O d. (AB): 10-->1--> 10 for anythingYou are given a 4-bit a comparator IC (7485). You have to verify the truth table for 4-bit comparator
- Construct a logical circuit of 64 × 1 multiplexer using 4 × 1 multiplexer.Question 3: Design a one-input, one-output serial 2's complementor. The circuit accepts a string of bits from the input and generates the 2's complement at the output. The circuit can be reset asynchronously to start and end the operation.Given in the figure is IC 7474 pin configuration. The pin connections of the IC is provided in the Table for the design of a particular counting sequence. What is that counting sequence for which it is desined. Intially the FFs states (AB) were reset to 00. 74LS74 Dual D-type Flip Flop D-type Flip-flop Two vcc CLR D CLK PR 14 13 U 12 1110 PR CLK CLR HCLK 아 CLR D CLK PR GND D-type Flip-flop One Table Signal Value VcC (Logic 1) PIN NUMBERS 1, 4, 10, 13 and 14 3 and 11 Connected with a common clock A A' 7 Ground (Logic 0) 8 B' 9 B Is connected with PIN 8 Is connected with PIN 5 2 12 21 O a. (AB): 00 --> 01 -->10 --> 11 --> 00 O b. (AB): 00 --> 10 --> 01 --> 11 --> 00 O c. (AB): 00 -->10 --> 11 --> 01 --> 00 O d. (AB): 00 --> 10 -->11 --> O1 --> 00