Identify a pair of gates that has its truth tables exactly opposite. Verify what would happen if the inputs of NAND and NOR gates are tied together and an input of “0” or “1” is given
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Identify a pair of gates that has its truth tables exactly opposite. Verify what would happen if the inputs of NAND and NOR gates are tied together and an input of “0” or “1” is given
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- i) Use an XOR gate and an AND gate to build a half adder and complete the truth table below. Take a picture/snapshot of your circuit and attach it here: ii) Join two half adders in part i) together to form a full adder and complete the truth table below. Take a picture/snapshot of your circuit and attach it here: iii) Join 4 full adders together to form a 4-bit ripple adder and perform the following operation. Provide screen shots of your circuits showing the corresponding binary inputs and outputs. iiii) Now, try implementing the full adder in Part ii) a) Provide screen shots of your circuits showing clearly the corresponding binary inputs and outputs for 1+1 in binary. State in this report clearly which are the inputs and outputs on the circuit board b) join two full adders together so that it can perform 2-bit addition and substraction. Provide screen shots of your circuits showing clearly the corresponding binary inputs and outputs for 01 + 11 and 10 – 01 in binary. State in this…If we want to design a logic circuit that make selective complement for example, to complement the first two-bits of the number (1010) to become (1001) O using XOR gate with 0011 O using OR gate with 1100 O using XNOR gate with 1011 O using AND gate with 1100if we want to design a logic * circuit that make selective complement for example, to complement the first three-bits of the number (1111) to become (1000) O using OR gate with 0111 O using XOR gate with 0111 O using AND gate with 0111 O using XNOR gate with 1111 nts
- Assume that the exclusive-OR gate has a contamination delay of 10 ns and that the AND or OR gates have a contamination delay of 5 ns. What is the total contamination delay time in the 8-bit adder? Note: your answer should include only the value of the delay without the unit (only the number) A B- Cin- Cout Answer:Q1: Design and implement an asynchronous counter that counts from 0000 up to 1100 (modulus 13). Use OR gate, and show in the drawing how the OR gate is connected to truncate the state 1101.• When a problem references the "gate table”, use the following table of gate information: Number of Transistors ted tpd 0.4 0.5 2.2 2.6 2.2 2.6 1.8 2.1 1.8 2.1 2.6 3.2 2.6 3.2 Gate NOT AND2 OR2 NAND2 NOR2 XOR2 XNOR2 2 6 6 4 4 8 8
- Q If we want to design a logic circuit that make selective set for example, the number (0001) to become (0111) O using XNOR gate with the same number as input O using XOR gate with the 0111 number as input using AND gate with the 0111 number as input using OR gate with the 0110 number as inputLogic Gates:* 7404LS (NOT)* 7408LS (AND)* 7432LS (OR)* 7400LS (NAND)* 7402LS (NOR)* 7486LS (EX-OR)Or you can use 74HCxx versions. Task 2: 4 INPUT PRIORITY ENCODERa) Write the truth table.b) Find the outputs in terms of min terms using minimal expression.c) By using K map, find the simple/simplest expression of theoutputs.d) Draw the circuit diagram. (Simulation design will be accepted.)e) Simulate the circuit & explain your results. (Please do notdesign separate simulations for each output. You should design ONEsimulation including all inputs and outputs.)Problem 6: Find the sizes of the transistors for the circuit below for the least delay from the input to the output. Label the sizes in the boxes for the single gates and besides the transistors in the figure for the compound gate OAI21 gate. Delay = G1 Р:2 27 N: 1 G2 G3 G4 P: N: P: N:
- The input to a combinational logic circuit is 4-bit binary number (A, B, C, D). Design the circuit strictly using NAND gate with two outputs (Y1 and Y2) for the following conditions: Output Y1 is low when the input binary number is less than or equal to 7. Output Y2 is high when the input binary number is less than or equal to 7.Problem 02: Equivalent to NAND Gate Draw an equivalent circuit to a three-input NAND gate using ouly one-input and two-input logic gates. Prove that your circuit is equivalent to a threo-input NAND gate.1. Why NAND and NOR gates are called the Universal gates? 2. What information is available on the data sheet for NAND gate? 3. If the 0 and 1 were inputs for a XOR gate, what would be the output? 4. If a signal passing through a gate is inhibited by sending a LOW into one of the inputs, and the output is LOW, the gate is an