I was wondering what the flaws of the OSI model were.
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I was wondering what the flaws of the OSI model were.
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- Are the VLIW and superscalar designs difficult to implement? Which architecture is more difficult to create a compiler for? Why?The connection between the CPU and memory might be either a synchronous or an asynchronous bus. Which one is more nimble and quick? Explain how you came to the conclusion you did.148 This is what you're going to do. Let's say that a RISC processor takes 2 microseconds to do each instruction, and that an I/O device can only wait 1 millisecond before its interrupt is handled. When interrupts are turned off, how many instructions can be run?
- Pick an architecture other than those covered in this chapter. Do research to find out how your architecture deals with the concepts introduced in this chapter, as was done for Intel and MIPS.Is there anything that prevents a reasonable trade-off between central processing unit, memory, bus, and peripheral performance?Should the CPU-memory bus be synchronous or asynchronous? Is it best-performing? Why that choice?
- Should the CPU-memory bus be synchronous or asynchronous? How did you decide?Suppose you wanted to implement a control unit for a computer that you are designing. A. Would you use a hardwired implementation or a micro-programmed control unit? Why? I would use a micro-programmed control unit for my computer. The reason for this is because micro-programmed control units are easier to handle and make modifications. Also, modern processors that utilize the CISC architecture can convert code to be more RISC-like to be used internally. B. What factors in the computer design would affect your decision? It depends on my intended plan for the device. If I were to design a personal computer for non-commercial use, I would more than likely implement micro-programmed control units. If I were to design microprocessors for use in embedded systems or mobile devices, I would use the hardwired control unit.Let's say, for the sake of simplicity, that a RISC processor executes each instruction in 2 microseconds and that an I/O device can only wait for an interrupt to be handled for a maximum of 1 millisecond before it is handled. Do you have any idea how many instructions can be run with interruptions disabled before they reach a certain number?