Execute the following program using (a) Stack Architecture Instruction Set (b) Accumulator Architecture Instruction Set (c) General Purpose Register Instruction Set (d) Using 0 address field (e) Using 1 address field (f) Using 2 address field (g) Using 3 address field F = R(C+D)-(RA+B)
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- A(n) ________________ instruction always alters the instruction execution sequence. A(n) ______________ instruction alters the instruction execution sequence only if a specified Condition is true.A(n) ____________________ instruction copies data from one memory location to another.Write down the control sequence for the instruction ADD R4,R5,R6 for three bus organizations in computer architecture
- The term Harvard architecture means(a) a CPU and a main memory(b) a CPU and two data memories(c) a CPU, a program memory, and a data memory(d) a CPU and two register filesDescribe the pipeline architecture in the context of ALU instruction execution.REAL MODE MEMORY ADDRESSING Find the memory location addressed by the microprocessor, when operated in the real mode, for the following segment register and 80286 register combinations: a) DS=8EBC & DX=A3D7 b) CS=DCAF & IP=FAC8
- An instruction is stored at location 300 with its address field at location 301. The address field has the value 400. A processor register R1 contains the number 200. Evaluate the effective address if the addressing mode of the instruction is (a) direct; (b) immediate; (c) relative; (d) register indirect; (e) index with R1 as the index register.Let us assume that we would like to design an ISA R-format instruction format for a processor. The processor has 256 registers and 64 opcodes. The R-format has four fields, the opcode and three fields for the registers. Show the instruction format and the bit allocation for each field.The instruction is stored at location 300 with its address field at location 301. The address field has a value of 400. A processor register R1 contains the number 200. Evaluate the effective address if the addressing mode of the instruction is Relative Addressing mode; • Relative: 300 + 200 = 500 • Relative: 302 + 200 = 502 • Relative: 301 + 400 = 701 • Relative: 302 + 400 = 702
- Enumerate the stages of instruction execution in a pipelined architecture.Identify the Offset Register/s needed by the Segment Register to have the Physical Address. Stack Segment Extra Segmenta) Programmable Read-Only Memory (PROM) is a computer memory chip which is programmable once it is created and the information cannot be erased Implement the following Boolean functions using PROM. F1(A1, A0) = F2(A1, A0) = m(3,5,7), m(4,5,7) Major Topic Programmable Read Only Memory (PROM) Major Topic Programmable Logic Array (PLA) b) A combinational circuit is defined by the function F1= Σ m (3,5,7), F2 = Σ m (4,5,7). Implement the circuit using a PLA which consists of 3 inputs (A, B and C), 3 product terms and two outputs Blooms Designation AP Major Topic Combinational Logic Circuits Blooms Designation AN Major Topic Memories Devices c) A combinational circuit has four inputs and one output, the output equal 1 when: 1 - all the inputs are equal to 1 or 2- non of the inputs are equal to 1 or 3- an odd number of inputs are equal to 1. Design the logic circuit. Blooms Designation AP d) Using the required steps convert a D flip-flop to T flip-flop Spore Blooms Designation AN Store Score…