During the execution of the beq instruction, what is the significance of the Zero output of the arithmetic and logical unit (ALU) circuit block in the MIPS single-cycle microarchitecture?
During the execution of the beq instruction, what is the significance of the Zero output of the arithmetic and logical unit (ALU) circuit block in the MIPS single-cycle microarchitecture?
Chapter6: System Integration And Performance
Section: Chapter Questions
Problem 33VE
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During the execution of the beq instruction, what is the significance of the Zero output of the arithmetic and logical unit (ALU) circuit block in the MIPS single-cycle microarchitecture?
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Complete MIPS SCμArch
PC'
CLK
Σ
PC
A
RD
Instruction
Memory
Adder
Instr
PCPlus4
31:26
5:0
Control
Unit
Opcode
Funct
25:21
20:16
20:16
15:11
15:0
CLK
A1
A2
A3
WD3
MemtoReg
MemWrite
Branch
ALUControl
ALUSrc
RegDst
RegWrite
WE3
RD1
Sign Extend
RD2
Register
File
Writeto Reg4:0
SignImm
0
1
0
1
SrcA
SrcB
<<2
ALU
Zero
ALUResult
Adder
PCBranch
PCSource
CLK
A
WE
WD
RD
Data
Memory
ReadData
0
1
Result
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