DataPath Performance Evaluation: Use the following information for all parts of the question. Please round your answers to 2 decimal places. Memory Access = 680 ps ALU Operations = 340 ps Register Access = 170 ps Note: for this exam, the critical data path for JUMP is just the Instruction Fetch stage. 1. If we implement the DataPath as a single-cycle using variable cycle length, fill in the cycle time for the following statement types (critical data path) in ps. R-Type:: Load Type = Store Type = Branch Type = Jump = = ps ps ps ps ps

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Chapter4: Processor Technology And Architecture
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Please help with this Computer architecture homework question.
DataPath Performance Evaluation: Use the following information for all parts of the question.
Please round your answers to 2 decimal places.
24:01 SIST
Memory Access = 680 ps
ALU Operations = 340 ps
Register Access = 170 ps
Note: for this exam, the critical data path for JUMP is just the Instruction Fetch stage.
1. If we implement the DataPath as a single-cycle using variable cycle length, fill in the cycle
time for the following statement types (critical data path) in ps.
R-Type: =
Load Type =
Store Type =
Branch Type =
ps
Load type=19%
Store type = 23%
Branch type=8%
Jump = 2%
ps
TYPE
R-Type
Load
Store
Branch
Jump
ps
ps
Jump =
2. If we implement the above DataPath using a single-cycle with fixed length, the cycle length
would be
ps.
3. If we are running a program with instruction mix:
R-type= 48%
ps
%age
the average time to execute an instruction is
Critical Time
notoulart
ps
Weighted Time
Transcribed Image Text:DataPath Performance Evaluation: Use the following information for all parts of the question. Please round your answers to 2 decimal places. 24:01 SIST Memory Access = 680 ps ALU Operations = 340 ps Register Access = 170 ps Note: for this exam, the critical data path for JUMP is just the Instruction Fetch stage. 1. If we implement the DataPath as a single-cycle using variable cycle length, fill in the cycle time for the following statement types (critical data path) in ps. R-Type: = Load Type = Store Type = Branch Type = ps Load type=19% Store type = 23% Branch type=8% Jump = 2% ps TYPE R-Type Load Store Branch Jump ps ps Jump = 2. If we implement the above DataPath using a single-cycle with fixed length, the cycle length would be ps. 3. If we are running a program with instruction mix: R-type= 48% ps %age the average time to execute an instruction is Critical Time notoulart ps Weighted Time
Memory Performance:
The following questions will refer to the same instruction mix as above, with the following the
additional information:
Processor Pl:
42% of all instructions are memory access instructions.
Level 1 Cache Access = 0.68 ns
Main Memory Access = 59 ns
12% of all memory access is a "miss".
9. The clock rate of the processor =
_cycles
10 The Average Memory Access Time for the given data =
11. The Average number of cycles for a memory access
12. Assuming that the base CPI = 1.0 cycles, and using the answer from #11, memolquio 110
ad bloow slova sno lo digasi orl
ns
the average time to complete an instruction for the program described =_
Now, consider processor P2, with the addition of a Level 2 Cache, with an access time of
4.3 ns and a "hit" rate of 13%.
GHz.
ii.nonto molami bonil
ns
13. The Average Memory Access Time for the given data =
14. The Average number of cycles for a memory access =
15. Assuming that the base CPI = 1.0 cycles, and using the answer from #14,
the average CPI for the program described
16. Which processor performs better for the program described? (P1 or P2)
nsomment scuse ori gried 2
ns for P2.
top-31
qy dommel
cycles
cycles and mustom asig on T
noliartedi buol od 1o A
17. Including the delays in the Pipelined DataPath in question 8, and the memory
performance analysis in question 15, find the
Average Memory Access =
18. Find the final average effective number of cycles for processor P2 =
19. Find the final average time to complete an instruction for processor P2 =
Jani 100
is endousad
Ino-stiupst
GODE
Transcribed Image Text:Memory Performance: The following questions will refer to the same instruction mix as above, with the following the additional information: Processor Pl: 42% of all instructions are memory access instructions. Level 1 Cache Access = 0.68 ns Main Memory Access = 59 ns 12% of all memory access is a "miss". 9. The clock rate of the processor = _cycles 10 The Average Memory Access Time for the given data = 11. The Average number of cycles for a memory access 12. Assuming that the base CPI = 1.0 cycles, and using the answer from #11, memolquio 110 ad bloow slova sno lo digasi orl ns the average time to complete an instruction for the program described =_ Now, consider processor P2, with the addition of a Level 2 Cache, with an access time of 4.3 ns and a "hit" rate of 13%. GHz. ii.nonto molami bonil ns 13. The Average Memory Access Time for the given data = 14. The Average number of cycles for a memory access = 15. Assuming that the base CPI = 1.0 cycles, and using the answer from #14, the average CPI for the program described 16. Which processor performs better for the program described? (P1 or P2) nsomment scuse ori gried 2 ns for P2. top-31 qy dommel cycles cycles and mustom asig on T noliartedi buol od 1o A 17. Including the delays in the Pipelined DataPath in question 8, and the memory performance analysis in question 15, find the Average Memory Access = 18. Find the final average effective number of cycles for processor P2 = 19. Find the final average time to complete an instruction for processor P2 = Jani 100 is endousad Ino-stiupst GODE
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