Consider a bus-based shared memory with two processors P and Q. Assume that X in memory was originally set to 5 and the following operations were performed in the order given:(1) P updates X; (2) Q reads X; (3) Q updates X; (4) Q reads X; (5) Q updates X;(6) P updates X; (7) Q reads X. Tabulate the Value and state of the memory, P's cache and Q's cache for the following protocols. i. Write- update Write-Through protocol ii. Write- Invalidate Write-Back protocol Updating X by processor P corresponds to the operation X= X+3, Updating X by processor C corresponds to the operation X= X - 3.

Consider a bus-based shared memory with two processors P and Q. Assume that X in memory was originally set to 5 and the following operations were performed in the order given:(1) P updates X; (2) Q reads X; (3) Q updates X; (4) Q reads X; (5) Q updates X;(6) P updates X; (7) Q reads X. Tabulate the Value and state of the memory, P's cache and Q's cache for the following protocols. i. Write- update Write-Through protocol ii. Write- Invalidate Write-Back protocol Updating X by processor P corresponds to the operation X= X+3, Updating X by processor C corresponds to the operation X= X - 3.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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