can determine the resulting input impedance. We find that we can model the input impedance using just the biasing chain, and ignoring the output transistors, as they reduce the current draw slightly. The input current drain is thus: So İin = −İB₁ + İB₂ = −/ic₁ + ic₂ VCC-Vin+VBE1₁ iin = ²/3 [- R₁ iin = == 2 Vin BR VEE-Vin+VBE₂ R₂ since Vcc The steps for calculating all the components required are summarised below. At this point, you will find that you might not be able to meet the required input impedance specifications. -VEE, VBE-VBE₁ = VBE₂, and R = R₁ = R₂. (4)

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Please show me the derivation of equation 1-4 with a reasonable assumption 

A
Class AB amplifier differs from a Class B amplifier in its midpoint operation, i.e. when input voltage
is equal or less than the p-n junction barrier potential. In a Class B amplifier, neither the 'push' nor the
'pull' transistors are active in this region, and therefore there is a (crossover) distortion around the
midpoint area. In a Class AB amplifier, both transistors are active in the midpoint region and this
removes the crossover distortion in the Class B amplifier with the trade-off of a higher quiescent
power. More details can be found in Sec. 13-1-13.3 of Sedra and Smith.
1 kHz
VBE
Ic = Ise VT
Vin
C₁
HI
IC₁ IR₁
=
+12V
-12V
VCC-VE₁
R₁
Ri
=
Q₁
-12V
+12V
Q₂
R 2
Vcc-VB,+VBEı
R₁
V₂
Q3
R3
0.47 Ω
R4
0.47 Ω
24
Figure 1 Class AB amplifier
There are two stages in our design of the power amplifier. We will first start with a simple Class AB
push pull amplifier with a matched transistor bias stage (Figure 1). In this circuit, if the transistors are
assumed to have the same saturation current, Is, then the quiescent collector currents of all the
transistors will be the same (we also assume the voltages across R3 and R4 are negligible).
C₂
#||
(1)
The collector current of Q₁ determines the base-emitter voltage, and that is the same as the base-
emitter voltage of Q3, and thus the collector current of Q3 is the same as Q₁. This means that we can
control the quiescent current and thus bias the output transistors by changing R₁ and R₂.
Vout
Again assuming that we have matched transistors, we can assume that the push (top) and pull (bottom)
parts of the circuits are complementary during steady state, such that VB = 0 for Q1 and Q2, and
Vout = 0. Therefore we have for Q1,
-12V
(2)
with VBE = -0.7 V. Thus we can control and reduce the quiescent currents through Q₁ to Q4 by increasing
R₁ and R₂. However, the upper limit of the resistance is determined by the maximum base current
required by Q3 (and similarly for Q4).
(3)
VCC-VB₁ +VBE₁> İB₂ = C3
iR₁
R₁
with the maximum current when the input signal is at its peak. That is, max (Vin) = max (VÂ₁) = 8V,
max(ic) = 1A. This gives the upper limit for R₁ and R₂. Now that we have the biasing resistors, we
RL
8.2 Ω
Transcribed Image Text:A Class AB amplifier differs from a Class B amplifier in its midpoint operation, i.e. when input voltage is equal or less than the p-n junction barrier potential. In a Class B amplifier, neither the 'push' nor the 'pull' transistors are active in this region, and therefore there is a (crossover) distortion around the midpoint area. In a Class AB amplifier, both transistors are active in the midpoint region and this removes the crossover distortion in the Class B amplifier with the trade-off of a higher quiescent power. More details can be found in Sec. 13-1-13.3 of Sedra and Smith. 1 kHz VBE Ic = Ise VT Vin C₁ HI IC₁ IR₁ = +12V -12V VCC-VE₁ R₁ Ri = Q₁ -12V +12V Q₂ R 2 Vcc-VB,+VBEı R₁ V₂ Q3 R3 0.47 Ω R4 0.47 Ω 24 Figure 1 Class AB amplifier There are two stages in our design of the power amplifier. We will first start with a simple Class AB push pull amplifier with a matched transistor bias stage (Figure 1). In this circuit, if the transistors are assumed to have the same saturation current, Is, then the quiescent collector currents of all the transistors will be the same (we also assume the voltages across R3 and R4 are negligible). C₂ #|| (1) The collector current of Q₁ determines the base-emitter voltage, and that is the same as the base- emitter voltage of Q3, and thus the collector current of Q3 is the same as Q₁. This means that we can control the quiescent current and thus bias the output transistors by changing R₁ and R₂. Vout Again assuming that we have matched transistors, we can assume that the push (top) and pull (bottom) parts of the circuits are complementary during steady state, such that VB = 0 for Q1 and Q2, and Vout = 0. Therefore we have for Q1, -12V (2) with VBE = -0.7 V. Thus we can control and reduce the quiescent currents through Q₁ to Q4 by increasing R₁ and R₂. However, the upper limit of the resistance is determined by the maximum base current required by Q3 (and similarly for Q4). (3) VCC-VB₁ +VBE₁> İB₂ = C3 iR₁ R₁ with the maximum current when the input signal is at its peak. That is, max (Vin) = max (VÂ₁) = 8V, max(ic) = 1A. This gives the upper limit for R₁ and R₂. Now that we have the biasing resistors, we RL 8.2 Ω
can determine the resulting input impedance. We find that we can model the input impedance using
just the biasing chain, and ignoring the output transistors, as they reduce the current draw slightly.
The input current drain is thus:
İin = −İß₂ + İB₂ = −/ic₁ + ic₂
Vcc-Vin+VBE1
iin = 1/[²
R₁
iin
So
2 Vin
BR
since Vcc= -Vee, Vbe = −1
-VBE₁ =
VEE-Vin+VBE₂
R₂
VBE₂, and R = R₁ = R₂.
(4)
The steps for calculating all the components required are summarised below. At this point, you will
find that you might not be able to meet the required input impedance specifications.
Transcribed Image Text:can determine the resulting input impedance. We find that we can model the input impedance using just the biasing chain, and ignoring the output transistors, as they reduce the current draw slightly. The input current drain is thus: İin = −İß₂ + İB₂ = −/ic₁ + ic₂ Vcc-Vin+VBE1 iin = 1/[² R₁ iin So 2 Vin BR since Vcc= -Vee, Vbe = −1 -VBE₁ = VEE-Vin+VBE₂ R₂ VBE₂, and R = R₁ = R₂. (4) The steps for calculating all the components required are summarised below. At this point, you will find that you might not be able to meet the required input impedance specifications.
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