(c) Design a synchronous counter using J-K flip-flop that can be used for an elevator system of a 7th story building as shown in Figure 4. Assume that the ground level is considered as a 0th floor. Assume that level 2 and level 4 cannot be accessed since it is for the authorized person only. Provide the logic circuit design with the minimum number of logic gates.

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answer question 2.c quickly (please answer in 1 hour only) thank you very much
(c) Design a synchronous counter using J-K flip-flop that can be used for an elevator
system of a 7th story building as shown in Figure 4. Assume that the ground level is
considered as a 0th floor. Assume that level 2 and level 4 cannot be accessed since it
is for the authorized person only. Provide the logic circuit design with the minimum
number of logic gates.
[Reka bentuk pembilang segerak menggunakan J-K flip-flop yang boleh digunakan untuk sistem lif
bangunan tingkat 7 seperti yang ditunjukkan dalam Rajah 4. Andaikan aras tanah dianggap sebagai
tingkat 0. Andaikan tingkat 2 dan tingkat 4 tidak boleh diakses kerana ia adalah untuk orang yang
diberi kuasa sahaja. Sediakan reka bentuk litar logik dengan bilangan get logik minimum.]
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6
5
4
3
1
Figure 4
[Rajah 4]
ㅇ
Transcribed Image Text:(c) Design a synchronous counter using J-K flip-flop that can be used for an elevator system of a 7th story building as shown in Figure 4. Assume that the ground level is considered as a 0th floor. Assume that level 2 and level 4 cannot be accessed since it is for the authorized person only. Provide the logic circuit design with the minimum number of logic gates. [Reka bentuk pembilang segerak menggunakan J-K flip-flop yang boleh digunakan untuk sistem lif bangunan tingkat 7 seperti yang ditunjukkan dalam Rajah 4. Andaikan aras tanah dianggap sebagai tingkat 0. Andaikan tingkat 2 dan tingkat 4 tidak boleh diakses kerana ia adalah untuk orang yang diberi kuasa sahaja. Sediakan reka bentuk litar logik dengan bilangan get logik minimum.] 7 6 5 4 3 1 Figure 4 [Rajah 4] ㅇ
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