By convention, a cache is named according to the amount of data it contains (ie., a 4 KiB cache can hold 4 KiB of data); however, caches also require SRAM to store metadata such as tags and valid bits. For this exercise, you will examine how a cache's configuration affects the total amount of SRAM needed to implement it as well as the performance of the cache. For all parts, assume that the caches are byte addressable, and that addresses and words are 64 bits. 1. Calculate the total number of bits required to implement a 32 KiB cache with two-word blocks. 2. Calculate the total number of bits required to implement a 64 KiB cache with 16-word blocks. How much bigger is this cache than the 32 KiB cache described in Exercise (1) above? (Notice that, by changing the block size, we doubled the amount of data without doubling the total size of the cache.) 3. Explain why this 64 KiB cache, despite its larger data size, might provide slower performance than the first cache. 4. Generate a series of read requests that have a lower miss rate on a 32 KiB two-way set associative cache than on the cache described in Exercise (1) above.

By convention, a cache is named according to the amount of data it contains (ie., a 4 KiB cache can hold 4 KiB of data); however, caches also require SRAM to store metadata such as tags and valid bits. For this exercise, you will examine how a cache's configuration affects the total amount of SRAM needed to implement it as well as the performance of the cache. For all parts, assume that the caches are byte addressable, and that addresses and words are 64 bits. 1. Calculate the total number of bits required to implement a 32 KiB cache with two-word blocks. 2. Calculate the total number of bits required to implement a 64 KiB cache with 16-word blocks. How much bigger is this cache than the 32 KiB cache described in Exercise (1) above? (Notice that, by changing the block size, we doubled the amount of data without doubling the total size of the cache.) 3. Explain why this 64 KiB cache, despite its larger data size, might provide slower performance than the first cache. 4. Generate a series of read requests that have a lower miss rate on a 32 KiB two-way set associative cache than on the cache described in Exercise (1) above.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter11: Operating Systems

Section: Chapter Questions

Problem 2VE

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By convention, a cache is named according to the amount of data it contains (i.e., a 4 KiB cache can hold 4 KiB of data); however, caches also require SRAM to store metadata such as tags and valid bits. For this exercise, you will examine how a cache's configuration affects the total amount of SRAM needed to implement it as well as the performance of the cache. For all parts, assume that the caches are byte addressable, and that addresses and words are 64 bits. (a) Calculate the total number of bits required to implement a 32 KiB cache with two-word blocks. (b) Calculate the total number of bits required to implement a 64 KiB cache with 16-word blocks. How much bigger is this cache than the 32 KiB cache described in Part a? (Notice that, by changing the block size, we doubled the amount of data without doubling the total size of the cache.)
In general, a cache is named according to the amount of data it contains (i.e., a 4 KiB cache can hold 4 KiB of data); however, caches also require SRAM to store metadata such as tags and valid bits. You design this cache memory and will examine how a cache's configuration affects the total amount of SRAM needed to implement it as well as the performance of the cache. For all parts, assume that the that addresses and words are 64 bits. (A) Calculate the total number of bits required to implement a 32 KiB cache with two-word blocks. (B) Calculate the total number of bits required to implement a 96 KiB cache with 16-word blocks. How much bigger is this cache than the 32 KiB cache described in (A) above? (Notice that, by changing the block size, we increased the amount of data without doubling the total size of the cache.) (C) Explain why this 96 KiB cache, despite its larger data size, might provide slower performance than the first cache.
In general, a cache is named according to the amount of data it contains (i.e., a 4 KİB cache can hold 4 KiB of data); however, caches also require SRAM to store metadata such as tags and valid bits. You design this cache memory and will examine how a cache's configuration affects the total amount of SRAM needed to implement it as well as the performance of the cache. For all parts, assume that the that addresses and words are 64 bits. (A) Calculate the total number of bits required to implement a 32 KİB cache with two-word blocks. (B) Calculate the total number of bits required to implement a 96 KiB cache with 16-word blocks. How much bigger is thi cache than the 32 KiB cache described in (A) above? (Notice that, by changing the block size, we increased the amount of data without doubling the total size of the cache.) (C) Explain why this 96 KiB cache, despite its larger data size, might provide slower performance than the first cache.
Computer Science Consider a direct-mapped cache with 8 lines, each holding 16 bytes of data. The cache is byte-addressable and the main memory consists of 64 KB, which is also byte-addressable. Assume that a program reads 16KB of memory sequentially. Answer the following questions:a) How many bits are required for the tag, index, and offset fields of a cache address?b) What is the cache size in bytes?c) What is the block size in bytes?d) What is the total number of blocks in main memory?e) How many cache hits and misses will occur for the program, assuming that the cache is initially empty?f) What is the hit ratio?g) Give an example virtual address (in BINARY) that will be placed in cache line 5.
For a direct-mapped cache design with a 32-bit address, the following bitsof the address are used to access the cache. Use the table below. a. What is the cache block size (in words)?b. How many entries does the cache have?c. What is the ration between total bits required for such a cache implementation overthe data storage bit?
For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache: Tag Index Offset 31-10 9-6 5-0 1. What is the cache block size (in words)? 2. How many entries does the cache have? 3. What is the ratio between total bits required for such a cache implementation over the data storage bits?
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A cache memory system with capacity of N words and block size of B words is to be designed. If it is designed as a direct mapped cache, the length of the TAG field is 14 bits. If it is designed as a 4-way set associative cache, the length of the TAG field will be ………… bits.
For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. We assume that each word has 4 bytes. How many entries does the cache have? Tag Index Offset Block offset | Byte offset 31–12 11-6 5-2 1-0
Cache memory systems are designed such that the computer first checks the L1 cache for the desired memory. If the data is there, it accesses it and is done. It only checks the L2 cache if the data is not found in the L1 cache. Likewise, the computer checks the L3 cache if the desired data is not found in the L2 cache, and finally it on only checks main memory if the data is not found in the L3 cache. Imagine a computer system with the following cache access times: L1 cache: 3 processor cycles L2 cache: 10 processor cycles L3 cache: 25 processor cycles Main memory: 100 processor cycles So, in the best case, the desired data would be immediately found in the L1 cache, which requires only 3 cycles to check. Conversely, in the worst case, the desired data would only be in main memory, which would require 138 cycles to access (3 cycles to check L1 cache + 10 cycles to check L2 + 25 cycles to check L3 + 100 cycles to access main memory). What is important, however, is the average…
For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. Tag 31-10 Index 9-5 a. What is the cache block size (in words)? b. How many entries does the cache have? Offset 4-0 c. What is the ratio between total bits required for such a cache implementation over the data storage bits?
A direct-mapped cache consists of 16 blocks. A byte-addressable main memory contains 4K blocks of 16 bytes each. Access time for the cache is 30 ns and the time required to fill a cache slot from main memory is 250 ns. Assume a request is always started in sequential to cache and then to main memory. If a block is missing from cache, the entire block is brought into the cache and the access is restarted. Initially, the cache is empty. a) Show the main memory address format that allows us to map addresses from main memory to cache. Be sure to include the fields as well as their sizes. b) Compute the hit ratio for a program that loops 4 times from locations 0 to 42 (base 10) in memory. c) Compute the effective access time for this program.