ata dependence is identified by the stage that produces the result (EX or MEM) and the instruction that consumes the result (1st instruction that follows the one that produces the result, 2nd instruction that follows, or both). We assume that the register write is done in the first half of the clock cycle and that register reads are done in the se
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This exercise will help you understand the cost/complexity/performance tradeoffs of forwarding in a pipelined processor. Problems in this exercise refer to pipelined datapaths from Figure 4.45. These problems assume that, of all the instructions executed in a processor, the following fraction has a particular type of RAW data dependence. The type of RAW data dependence is identified by the stage that produces the result (EX or MEM) and the instruction that consumes the result (1st instruction that follows the one that produces the result, 2nd instruction that follows, or both). We assume that the register write is done in the first half of the clock cycle and that register reads are done in the second half of the cycle, so “EX to 3rd” and “MEM to 3rd” dependences are not counted because they cannot result in data hazards. Also, assume that the CPI of the processor is 1 if there are no data hazards.
| EX to 1st only | MEM to 1st only | EX to 2nd only | MEM to 2nd only | EX to 1st and MEM to 2nd | Other RAW dependencies |
| 15% | 20% | 5% | 15% | 10% | 10% |
EX to 1st only example MEM to 2nd only example
add $t0, $t1, $t2 lw $t0, 20($t1)
add $t3, $t0, $t4 add $t3, $t5, $t4
add $t6, $t0, $s0
MEM to 1st only example EX to 1st and MEM to 2nd only example
lw $t0, 20($t1) lw $t4, 24($t0)
add $t3, $t0, $t4 add $t9, $s0, $s4
add $s1, $t4, $t9
EX to 2nd only example Other RAW Dependence example
add $t0, $t1, $t2 add $t0, $t1, $t2
add $t3, $t5, $t4 add $s0, $t3, $s0
add $t6, $t0, $s0 addi $s1, $s1, 4
add $t3, $t0, $t4
If we use forwarding only from the MEM/WB pipeline register, what fraction of cycles are we stalling due to data hazards?
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