can someone help me with this problem 14 Amdahl's Law15161718 2s Complement19 Op1.1 DecIC (M)14Avg CPI1.9Ttl Cycles CPU Speed Exec Time(M)(GHz)(msec)2.4ICParallelizable (M)9.6OverheadIC (M)0.3Exec Timew/2 CoresCores (M) (msec)Total ICwith 2+Exec Time Exec Time Exec Timew/4 Cores w/8 Cores w/16(msec) (msec)Cores% of TimeSavedw/16Op1.2 Dec Sum1 Dec Op1.1 Bin Op1.2 Bin Sum1 Bin Overflow? Op2.1 Dec Op2.2 Dec Sum2 Dec Op2.1 Bin Op2.2 Bin Sum2 Bin Overflow? Op3.1 Dec Op3.2 Dec Sum3 Dec Op3.1 Bin 4. Amdahl's lawIf you deploy multiple CPUs to tackle a program that is able to run partly in parallel, how muchtime can you save in executing it with more than one CPU? This problem calculates thatanswer. Find the numbers you need in the spreadsheet, and calculate the rest.How many instructions do you start with (in milions):What is your average CPI?a. How many total cycles will this IC require (in millions):What is your CPU's speed (GHz)?b. What's the execution time of this IC? (in msec, 2 digits past the decimal)What is the IC that can be run in parallel (in millions)?What is your extra "overhead" IC that must be added when running in parallel (in millions)?c. Finally, what's the total IC when running your program on more than a single core (inparallel, in millions):d. Now to calculate the savings. Calculate the run time for 2, 4, 8, and 16 cores. Remember,only the instructions that can be run in parallel will ever see the additional cores. The rest ofthe code (including the overhead instructions) will run serially on a single core.Answer in msec, 2 digits past the decimal.Cores4Exec Time(msec)16How much time did you save running on 16 cores? Calculate the time saved + originaltime, then convert to a %. Answer to the hundredths of a percent (e.g. 14.67%):

Parallel computing primarily uses Amdahl's Law to predict the theoretical maximum speed of a…

Amdahl's Law 2s Complement Op1.1 Dec IC (M) 14 Avg CPI 1.9 Ttl Cycles CPU Speed Exec Time (M) (GHz) (msec) 2.4 IC Paralleliz Overhead able (M) IC (M) 0.3 9.6 Total IC with 2+ Cores (M) Exec Time w/2 Cores (msec) Exec Time w/4 Cores (msec) Exec Time w/8 Cores (msec) Exec Time w/16 Cores % of Time Saved w/16 Op1.2 Dec Sum1 Dec Op1.1 Bin Op1.2 Bin Sum1 Bin Overflow? Op2.1 Dec Op2.2 Dec Sum2 Dec Op2.1 Bin Op2.2 Bin Sum2 Bin Overfl

Amdahl's Law 2s Complement Op1.1 Dec IC (M) 14 Avg CPI 1.9 Ttl Cycles CPU Speed Exec Time (M) (GHz) (msec) 2.4 IC Paralleliz Overhead able (M) IC (M) 0.3 9.6 Total IC with 2+ Cores (M) Exec Time w/2 Cores (msec) Exec Time w/4 Cores (msec) Exec Time w/8 Cores (msec) Exec Time w/16 Cores % of Time Saved w/16 Op1.2 Dec Sum1 Dec Op1.1 Bin Op1.2 Bin Sum1 Bin Overflow? Op2.1 Dec Op2.2 Dec Sum2 Dec Op2.1 Bin Op2.2 Bin Sum2 Bin Overfl

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 4PE

See similar textbooks

Similar questions

Processor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one cycle to complete, assuming zero wait state memory accesses. Processor C is a CISC processor with a 1.8 GHz clock rate. The average simple instruction requires one cycle to complete, assuming zero wait state memory accesses. The average complex instruction requires two cycles to complete, assuming zero wait state memory accesses. Processor R can’t directly implement the complex processing instructions of Processor C. Executing an equivalent set of simple instructions requires an average of three cycles to complete, assuming zero wait state memory accesses. Program S contains nothing but simple instructions. Program C executes 70% simple instructions and 30% complex instructions. Which processor will execute program S more quickly? Which processor will execute program C more quickly? At what percentage of complex instructions will the performance of the two processors be equal?
Why RISC processors have simple instructions taking about one clock cycle. The average clock cycle per instruction (CPI) is 1.5
The x86 instruction set architecture is an example of RISC. True False
A RISC instruction pipeline has five stages with propagation delays of 20 ns, 25 ns, 20ns, 70 ns, and 40 ns, respectively. What is the clock period? If a non-pipelined CPU can process an instruction in 160 ns, what is the actual steady-state speedup of the pipeline?
Compare Intel Quark SE C1000, PIC32MX795F512H, and AT32UC3A1512 microcontrollers in terms of the manufacturing company, CPU type, max speed (MHz), program memory Size (KB), SRAM size (KB), EEPROM size (KB), and used applications. Support your answer using figure/diagram
A program consists of 100,000 instructions as follows: Type of Instruction, IC, and CPI Instruction Type Integer arithmetic 48,000 Data transfer Instruction Count Floating-point arithmetic 32,000 12,000 Control transfer 8,000 4 5 10 3 Cycles per Instruction Determine the program execution time, the effective CPI for the machine, and the MIPS rate for the following processors. (each box is 2 points except CPI)
A common bus in a computer connects 16 source registers (each register is 32 bits) and one memory unit with word size of 32 bits also. If the bus is designed using multiplexers, answer the following: • What is the minimum number of multiplexers required? What is the minimum number of select lines each multiplexer has? If the bus is designed with three-state buffers and decoders, answer the following: • What is the minimum number of three-state buffers required? • What is the minimum number of decoders required? • What is the minimum size of each decode
A Multiple Instruction, Multiple Data (MIMD) system is one in which No RAM exists each processor executes the same instructions on different data each processor has its own stream of instructions, but these can be synchronized One processor executes instructions on different sets of data
Interfacing: Memory with 8051 O Design a 8051 micro controller with following specification 8051 CPU at 12 MHz * 32kB Program memory (ROM) * 16KB Data memory (RAM)
To keep up with Moore's Law and improve speed, a CPU would need to have more cores.
Design an interface between 8086 CPU and two chips of 16K X 8 EPROM and
For a second benchmark, libquantum, assume an execution time of 960 ns, CPI of 1.61, and clock rate of 3 GHz. If the execution time is reduced by an additional 10% without affecting to the CPI and with a clock rate of 4 GHz, determine the number of instructions.