(a) two NAND gates (b) two AND gates
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Realize a full subtracter using a 3-to-8 line decoder with inverting outputs and
(a) two NAND gates
(b) two AND gates
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- Q2: For BCD code perform the following, with and without complement: 1. 1000010110 is subtracted from 10101000001. 2. 759 be subtracted from 645.Design a combinational circuit with 3 inputs and 1 output. The output must be logic 1 when the binary value of the inputs have more 1’s than 0’s and logic 0 otherwise. Use only NAND Gates. (show All the steps)Assume that the exclusive-OR gate has a contamination delay of 10 ns and that the AND or OR gates have a contamination delay of 5 ns. What is the total contamination delay time in the 8-bit adder? Note: your answer should include only the value of the delay without the unit (only the number) A B- Cin- Cout Answer:
- 1. Assuming the full adder drives a load L=1.5, determine the critical path and its corresponding delay.2. Using this full adder to create an 8-bit ripple carry adder, what is the critical path delay of this 8-bit adder? (Assume unconnected ports are driving L=1.5 load)5- Determine an alternative method for implement the full-adder. Hint: Write the expressions of the circuit and simplify using icarnaugh map.Then implement using AND-OR gates. 6- Design a logic cct using NAND gate and convert BCD code to Excess-3code.2-to-1 multiplexers with an active high output and active high enable are to be used in the following implementations: (a) Show how to implement a 4-to-1 multiplexer with an active high output and no enable using two of the 2-to-1 MUXes and a minimum number of additional gates. (b) Repeat part (a) for a 4-to-1 multiplexer with an active low output. (c) Repeat part (b) assuming the output of the 2-to-1 MUX is 1 (rather than 0) when the enable is 0.
- i. Write the uses of half adder and full adder. ii. What do you understand by carry in addition? ii. Write the names of any two ICs available in market, for 4-bit full-adder.middle 4 digit letter 7 segment output 5206 EhJ EhJ5206 print that specific combination using one 7 segment display in a serial. the following should be included in the report. 1-- truth table 2--circuit =>general sop and pos =>simplified sop and pos =>using nand and nor gate =>using decoder =>using multiplexer 3-- conclusion and discussionQuestion 3: PLDS & Gate Delay 1. Consider the below PAL. Find the logic expression of the outputs W, X and Y. Do not simplify. **
- d) Draw the schematics of 4-bit synchronous and asynchronous MOD-8 counters and comment on their pros and cons. e) Calculate the noise margin for a logic gate with the following logic levels: VIL = 1.1 V, VIH = 3.2 V, VOL = 0.6 V, VOH = 4.0 V.1. What is the modulo of the circuit below? 2. Make a table of the count sequence. 3. A BCD counter can assume____discrete state. 4. A BCD counter can divide its input frequency by____. 5. A four-bit binary counter contains the number 0100. Nine inpulse occur. The new counter state is_____. 6. Design a 4-bit down counter.For the connections shown below, the equivalent logic gate is a) OR gate b) AND gate c) XOR gate d) NAND gate