A program contains 50% arithmetic/logic instructions, 30% load/store, 20% control transfer instructions. For a processor, the ideal CPIs for each of the three classes of instructions are 1, 5, 4, respectively. The only data accesses are loads and stores. If the miss penalty is 500 clock cycles and the miss rate is 5% for I-Cache and 6% for D-cache, how much faster would the computer be if all instructions were cache hits?
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- The time it takes to perform the fetch instruction and decode instruction steps is called the execution time. True or false?A(n) ________________ instruction always alters the instruction execution sequence. A(n) ______________ instruction alters the instruction execution sequence only if a specified Condition is true.A cache has a hit time Tc = 2 cycles and a miss rate Pmiss = 0.04. The main memory access time is Tmm = 36 cycles. The data-cache and instruction-cache have identical performance. A program has the following instruction distribution: probability of 0.3 for R-type instructions, 0.2 for load, 0.1 for store, and others for control instructions. Assume control instructions do not cause any loss. The processor is running at 1 GHz. Evaluate the average access time in nano-seconds of the memory system.
- A microprocessor has an increment memory direct instruction, which adds 1 to the value in a memory location. The instruction has five stages: fetch opcode(four bus clock cycles),fetch operand address (three cycles), fetch operand (three cycles) add 1 to operand (three cycles), and store operand (three cycles). a. By what amount (in percent) will the duration of the instruction increase if we have to insert two bus wait states in each memory read and memory write operation? b. repeat assuming that the increment operation takes 13 cycles instead of 3 cyclesAssume the miss rate of an instruction cache is 4% and the miss rate of the data cache is 5%. If a processor has a CPI of 3 without any memory stalls, and the miss penalty is 50 cycles for all misses, determine how much faster a processor would run with a perfect cache that never missed. Assume the frequency of all loads and stores is 44%.A program sees a 4% miss rate on both the Instruction Cache and the Data Cache. Every instruction requires access to the Instruction cache. Only 35% of the instructions require data access from the Data Cache. The miss penalty for either the data or the instruction cache is 100 cycles. Assume the average Clocks per Instruction (CPI) is 2 without any memory stalls (this is a hypothetical machine where if there were no misses on that instruction, it would get executed in 2 clock cycles. We are not worrying about how it is implemented, just, that suppose it was possible). Assume the number of instructions in a program is X. F1: What is the number of 'instruction miss cycles'? (The number of clock cycles lost due to a miss on the Instruction Cache) F2: What is the number of 'data miss cycles'? F3: What is the total run time of the program including the missed cycles dues to data and instruction misses?
- A program sees a 4% miss rate on both the Instruction Cache and the Data Cache. Every instruction requires access to the Instruction cache. Only 35% of the instructions require data access from the Data Cache. The miss penalty for either the data or the instruction cache is 100 cycles. Assume the average Clocks per Instruction (CPI) is 2 without any memory stalls (this is a hypothetical machine where if there were no misses on that instruction, it would get executed in 2 clock cycles. We are not worrying about how it is implemented, just, that suppose it was possible). Assume the number of instructions in a program is X. F1: What is the number of 'instruction miss cycles'? (The number of clock cycles lost due to a miss on the Instruction Cache) F2: What is the number of 'data miss cycles'? F3: What is the total run time of the program including the missed cycles dues to data and instruction misses? F4: What is the ratio of the actual run time (from question F3 above) to the…A program sees a 4% miss rate on both the Instruction Cache and the Data Cache. Every instruction requires access to the Instruction cache. Only 35% of the instructions require data access from the Data Cache. The miss penalty for either the data or the instruction cache is 100 cycles. Assume the average Clocks per Instruction (CPI) is 2 without any memory stalls (this is a hypothetical machine where if there were no misses on that instruction, it would get executed in 2 clock cycles. We are not worrying about how it is implemented, just, that suppose it was possible). Assume the number of instructions in a program is X. F3: What is the total run time of the program including the missed cycles dues to data and instruction misses? F4: What is the ratio of the actual run time (from question F3 above) to the fictitious run time if there were no cache misses at all?in 80886 microprocessor Suppose that. DS = 0200H, BX = 0300H, and DI-400H Determine the memory address accessed by each of the following instructions, assuming real mode operation: (1) MOV AL,[1234H] (2) MOV AX,[BX] (3) MOV [DI]AL
- Computer Science The total ISR instruction count for interrupt A, interrupt B, and interrupt C are 75, 105, and 80 instructions, respectively. Interrupt A occurs thrice as often as interrupt B, while interrupt C is called once whenever the other interrupts are called. If our microcontroller executes 60 million instructions per second and the combined CPU percentage of the three interrupts is 10% assuming they do not interrupt each other. What is the CPU overhead of interrupt A alone? (Answer as a percentage rounded off to two decimal places e.g. 12.345% is entered as 12.35) A timer was configured to generate an interrupt with a prescaler of 8 and a period register of 311. The ISR for the timer interrupt takes 73 instruction cycles in total, including context save and restore. If the instruction frequency is 8 MHz and the timer operates continuously, what is the percentage of CPU time used for the ISR? Note: Assume 1 additional cycle between timer rollovers and answer in percentage…Tompute the physical address for the specified operand in each of the following instructions. egister contents and variable are as follows: (CS)=0A00H, (DS)=OB0OH, (SS)=OD00H, S)=OFFOH, (DI)=00BOH, (BP)=00EAH and (UP)=0000H, LIST=00FOH, AX=4020H, BX=2500H. 1) Destination operand of the instruction MOV LIST (BP+DI], AX 2) Source operand of the instruction MOV CL, [BX+200H] 3) Destination operand of the instruction MOV [DI+6400H], DX 4) Source operand of the instruction MOV AL, [BP+SI-400H] 5) Destination operand of the instruction MOV [DI+SP], AX 6) Source operand of the instruction MOV CL, [SP+200H] 7) Destination operand of the instruction MOV [BX+DI+6400H], CX 8) Source operand of the instruction MOV AL , [BP-0200H] 9) Destination operand of the instruction MOV [SI], AX 10) Destination operand of the instruction MOV [BX][DI]+0400H,AL 11) Source operand of the instruction MOV AX, [BP+200H] 12) Source operand of the instruction MOV AL, [SI-0100H] 13) Destination operand of the…Consider a computer with cache, DRAM, HDD memory hierarchy. The hit rate of cache is 90% and DRAM is 95%. Read latencies of cache, DRAM, and HDD are 5ns, 100ns, and 1ms respectively. What is the average latency of executing an instruction involving a memory read? Express your answer in micro-seconds. Round it to the nearest integer. Enter your answer here