A CPU is equipped with a cache. If it takes 5 ns to access the data from the cache and 60 ns to access data from the main memory. What should be the hit ratio if the effective memory access time is 8 ns? Answer=
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- Most Intel CPUs use the __________, in which each memory address is represented by two integers.A(n) __________ is a storage location implemented in the CPU.A CPU is equipped with a cache. If it takes 4 ns to access the data from the cache and 100 ns to access data from the main memory, what is the effective memory access time if the hit ratio is 90%? Answer = ns
- A CPU is equipped with a cache. If it takes 4 ns to access the data from the cache and 200 ns to access data from the main memory, what is the effective memory access time if the hit ratio is 95%?A CPU is equipped with a cache. Accessing a word takes 35 clock cycles if the data is not in the cache and 5 clock cycles if the data is in the cache. What should be the hit ratio if the effective memory access time is 8 clock cycles? Answer = %If a microprocessor has a 24 address lines and 16 data lines, then the memory address space of this microprocessor in Mbytes is:
- A CPU's clock rate is 4 GHz. This CPU's cache hit time is measured as 1 clock cycle, the miss penalty is 35 cycles. The cache hit rate is 80%. What's this CPU's average memory access time measured in ns?What is the size of the memory for the microprocessor if it has 24-bit address lines (bus)? Furthermore, give the starting address and the last address of the memory.A microprocessor has an increment memory direct instruction, which adds 1 to the value in a memory location. The instruction has five stages: fetch opcode(four bus clock cycles),fetch operand address (three cycles), fetch operand (three cycles) add 1 to operand (three cycles), and store operand (three cycles). a. By what amount (in percent) will the duration of the instruction increase if we have to insert two bus wait states in each memory read and memory write operation? b. repeat assuming that the increment operation takes 13 cycles instead of 3 cycles
- Suppose that you have a computer with a memory unit of 24 bits per word. In this computer, the assembly program's instruction set consists of 198 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory. a. How many bits are needed for the opcode? b. How many bits are left for the address part of the instruction? c. How many additional instructions could be added to this instruction set without exceeding the assigned number of bits? Discuss and show your calculations.A computer has a 256K word addressable memory Module with 16 bits per word. The instruction set consists of 166 different instructions. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory. Based on the above, answer the following questions: a. How many bits are there in the main memory? (Represent it in power of 2) b. How many bits are needed for the opcode? c. How many bits are left for the address part of the instruction? d. How many additional instructions can be added to the existing 166 without affecting the assigned size of the opcode part? Justify.Question 6 Suppose you have a RISC machine with a 1.6 GHz clock (i.e., the clock ticks 1.6 billion times per second). This particular computer uses an instruction cache, a data cache, an operand fetch unit, and an operand store unit. The instruction set includes simple instructions with the following timings: set reg, immed 2 clock cycle 2 clock cycles 2 clock cycle 4 clock cycles 3 clock cycles loop label add reg, immed add reg, reg load reg, mem Assume that the following code franent is used to sum the element of a numeric array. If the initialization code has already executed (i.e. the SET instructions have already finished execution) how many array elements can be processed in 5 ms? Round your answer to the nearest integer. Recall that 1 ms = 0.001 seconds. Also assume that there are no physical memory limitations, implying that the array can be as large as desired. ri, e r2, MAX_SIZE ;initialize loop counter r3, @list initialize sum set set set initialize array pointer more: load…