A complete 6-stage non-pipelined 16-bit CPU architecture include 6 components: a register file, a decoder, an ALU, a control unit, a program counter, and ram/memory. Brief overview: opcode is 4 bits 14 different instructions implemented 8 general purpose registers RRR-type instructions are the largest, and take up 9 bits in register addresses 1 bit is a condition bit 2 bits unused simulated clock runs at a 10ns period or 100Mhz simulated memory is 512 bytes Referring to the 3 components as in the picture, namely the File Register, Decoder and ALU, you are required to describe how the three components operate.
A complete 6-stage non-pipelined 16-bit CPU architecture include 6 components: a register file, a decoder, an ALU, a control unit, a program counter, and ram/memory. Brief overview: opcode is 4 bits 14 different instructions implemented 8 general purpose registers RRR-type instructions are the largest, and take up 9 bits in register addresses 1 bit is a condition bit 2 bits unused simulated clock runs at a 10ns period or 100Mhz simulated memory is 512 bytes Referring to the 3 components as in the picture, namely the File Register, Decoder and ALU, you are required to describe how the three components operate.
Chapter8: Advanced Method Concepts
Section: Chapter Questions
Problem 7RQ
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A complete 6-stage non-pipelined 16-bit CPU architecture include 6 components: a register file, a decoder, an ALU, a control unit, a program counter, and ram/memory.
Brief overview:
- opcode is 4 bits
- 14 different instructions implemented
- 8 general purpose registers
- RRR-type instructions are the largest, and take up 9 bits in register addresses
- 1 bit is a condition bit
- 2 bits unused
- simulated clock runs at a 10ns period or 100Mhz
- simulated memory is 512 bytes
Referring to the 3 components as in the picture, namely the File Register, Decoder and ALU, you are required to describe how the three components operate.
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