A 64 KB four-way set-associative cache is byte- addressable and contains 32B lines. Memory addresses are 32b wide. a. Show at least Five main memory block addresses those are mapped to set number 5? b. Find hit/miss for following addresses 01010100011110001100011101000011 (5478C743H) 01010100011110001100011101100011 (5478C763H) 01010100011110001100011101010011 (5478C753H) 01010100011110001100011101001011 (5478C74BH)

A 64 KB four-way set-associative cache is byte- addressable and contains 32B lines. Memory addresses are 32b wide. a. Show at least Five main memory block addresses those are mapped to set number 5? b. Find hit/miss for following addresses 01010100011110001100011101000011 (5478C743H) 01010100011110001100011101100011 (5478C763H) 01010100011110001100011101010011 (5478C753H) 01010100011110001100011101001011 (5478C74BH)

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter6: System Integration And Performance

Section: Chapter Questions

Problem 22VE

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A 64 KB four-way set-associative cache is byte addressable and contains 32B lines. Memory addresses are 32b wide. a. Show at least Five main memory block addresses those are mapped to set number 5? b. Find hit/miss for following addresses 01010100011110001100011101000011 (5478C743H) 01010100011110001100011101100011 (5478C763H) 01010100011110001100011101010011 (5478C753H) 01010100011110001100011101001011 (5478C74BH)
3. The table below represents five lines from a cache that uses fully associative mapping with a block size of 8. Identify the address of the shaded data, 0xE6, first in binary and then in hexadecimal. The tag numbers and word id bits are in binary, but the content of the cache (the data) is in hexadecimal. Word id bits Tag 000 001 010 011 100 101 110 111 ------------------------------------------ 1011010 10 65 BA 0F C4 19 6E C3 1100101 21 76 CB 80 D5 2A 7F B5 0011011 32 87 DC 91 E6 3B F0 A6 1100000 43 98 ED A2 F7 4C E1 97 1111100 54 9A FE B3 08 5D D2 88
A cache is set up with a block size of 32 words. There are 64 blocks in cache and set up to be 4-way set associative. You have byte address 0x8923. Show the word address, block address, tag, and index Show each access being filled in with a note of hit or miss. You are given word address and the access are: 0xff, 0x08, 0x22, 0x00, 0x39, 0xF3, 0x07, 0xc0.
In a microprocessor of 32 bit addresses, the tag length will change if we design a two-way set-associate cache versus a four-way set-associative cache, with the same number of cache lines in each organization, and the same number of data bytes per set. a. True b. False
Suppose we have a byte-addressable computer using 2-way set associative mapping with 16-bit main memory addresses and 32 bits, the blocks of cache. Suppose also that each block contains 8 bytes. The size of the block offset field is bits, and the size of the tag field is bits. size of the set field is
Question 18 Suppose we have a byte-addressable computer using 2-way set associative mapping with 16-bit main memory addresses and 32 blocks of cache. Suppose also that each block contains 8 bytes. The size of the block offset field is bits, the bits. size of the set field is bits, and the size of the tag hield is
Given that a 4-way set associative cache memory has 64 KB data and each block contains 32 bytes. The main memory capacity is 4 GB. a. Find the number of bits for the main memory address. ANSWER: bits b. How many blocks are there in a set? ANSWER: blocks c. How many sets the cache has? ANSWER: d. The main memory address format is => | Tag: e. Which set will be mapped by the main memory address 458195h. ANSWER: sets bits | Set: bits | Word: bits | (in decimal)
A computer system has a 128 byte cache. It uses four-way set-associative mapping with 8 bytes in each block. The phy 32 bits, and the smallest addressable unit is 1 byte. (i) To what block frames of the cache can the address 000010AFH be assigned? (ii) If the addresses 000010AFH and FFFF7AXYH can be simultaneously assigned to the same Cache set, what values digits X and Y have?
Given that a 4-way set associative cache memory has 64 KB data and each block contains 32 bytes. The main memory capacity is 4 GB. a. Find the number of bits for the main memory address. ANSWER: b. How many blocks are there in a set? ANSWER: c. How many sets the cache has? ANSWER: d. The main memory address format is => | Tag: bits | blocks sets bits | Set: e. Which set will be mapped by the main memory address 458195h. ANSWER: decimal) bits bits | Word: (in
Given a 4-way set associative cache, which has 256 blocks and 64 bytes per block. Assume a 32-bit address. Calculate the following numbers: Part 1: How many bits are used for the byte offset? Answer = Part 2: How many bits are used for the set index? Answer = bits Answer bits Part 3: How many bits are used for the tag? bits
A cache memory has a line size of eight 64-bit words and a capacity of 4K words. The main memory size that is cacheable is 1024 Mbits. Assuming 4-way set associative mapping and that the addressing is done at the byte level. What is the format of the main memory addresses (i.e s-d, d, and w)? For the hexadecimal main memory location 2BFACEDH, find the corresponding 4-way set-associative memory format
The table below shows a 2-way set associative cache. What is the maximum size of the memory in Kbytes? First Way byte offset (binary) 01 Second Way byte offset (binary) Tag (binary) | (8 bits) Index Tag |(8 bits) | Valid Valid 00 10 11 00 01 10 11 000 AF 1 ВС 86 42 19 6D 1 7F B3 74 83 001 25 3B 69 FD 62 3B 1 D2 6C 68 DC 010 DO 1 44 53 23 62 C3 45 38 87 DA 011 15 1 83 13 48 AB 9B 1 41 8E 90 7A 100 DD 1 36 F4 ЕС ЕВ C5 1 7B ЕВ 41 69 101 4A 72 5B EA 8A 1A 34 3B 54 8E 110 8C 1 11 B1 C8 2E 4B 56 52 5B 27 11 55 A6 61 33 4B FO 48 СА А4 2E О а. 16 O b. 64 О с. 32 O d. 10 O e. 4 O f. 1 O g. 2 O h. 8 Clear my choice