9.31 (a) Find a minimum two-level NOR-gate circuit to realize F₁ and F₂. Use as many common gates as possible. F₁(a, b, c, d) = 2 m(1, 2, 4, 5, 6, 8, 10, 12, 14) F₂(a, b, c, d) = Σ m(2, 4, 6, 8, 10, 11, 12, 14, 15) (b) Realize F₁ and F₂ using a PLA. Give the PLA table and internal connection diagram for the PLA.
9.31 (a) Find a minimum two-level NOR-gate circuit to realize F₁ and F₂. Use as many common gates as possible. F₁(a, b, c, d) = 2 m(1, 2, 4, 5, 6, 8, 10, 12, 14) F₂(a, b, c, d) = Σ m(2, 4, 6, 8, 10, 11, 12, 14, 15) (b) Realize F₁ and F₂ using a PLA. Give the PLA table and internal connection diagram for the PLA.
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![9.31 (a) Find a minimum two-level NOR-gate circuit to realize F₁ and F₂. Use as many
common gates as possible.
F₁(a, b, c, d) = Σ m(1, 2, 4, 5, 6, 8, 10, 12, 14)
Σm(2, 4, 6, 8, 10, 11, 12, 14, 15)
F₂(a, b, c, d) =
(b) Realize F₁ and F₂ using a PLA. Give the PLA table and internal connection
diagram for the PLA.](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F6c921342-6d5a-48e4-a07c-a0e61e9e1942%2F0c6e7bfa-e0e6-4a0b-9d29-aec5ff1a80a2%2Fvtoh56n_processed.jpeg&w=3840&q=75)
Transcribed Image Text:9.31 (a) Find a minimum two-level NOR-gate circuit to realize F₁ and F₂. Use as many
common gates as possible.
F₁(a, b, c, d) = Σ m(1, 2, 4, 5, 6, 8, 10, 12, 14)
Σm(2, 4, 6, 8, 10, 11, 12, 14, 15)
F₂(a, b, c, d) =
(b) Realize F₁ and F₂ using a PLA. Give the PLA table and internal connection
diagram for the PLA.
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