5.1 In this exercise we look at memory locality properties of matrix computation. The following code is written in C, where elements within the same row are stored contiguously. Assume each word is a 32-bit integer. for (I-0: I<8: I++) for (J-0: J<8000: J++) A[1J[J]-B[I][0J+A[J][1]: 5.1.1 [5] <$5.1> How many 32-bit integers can be stored in a 16-byte cache block? 5.1.2 [5] <$5.l> References to which variables exhibit temporal locality? 5.1.3 (5] <$5.1> References to which variables exhibit spatial locality?
5.1 In this exercise we look at memory locality properties of matrix computation. The following code is written in C, where elements within the same row are stored contiguously. Assume each word is a 32-bit integer. for (I-0: I<8: I++) for (J-0: J<8000: J++) A[1J[J]-B[I][0J+A[J][1]: 5.1.1 [5] <$5.1> How many 32-bit integers can be stored in a 16-byte cache block? 5.1.2 [5] <$5.l> References to which variables exhibit temporal locality? 5.1.3 (5] <$5.1> References to which variables exhibit spatial locality?
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![5.1 In this exercise we look at memory locality properties of matrix computation.
The following code is written in C, where elements within the same row are stored
contiguously. Assume each word is a 32-bit integer.
for (I-0: I<8: I++)
for (J-0: J<8000: J++)
A[IJ[J]-B[I][0]+A[J][1]:
5.1.1 [5) <$5.l> How many 32-bit integers can be stored in a 16-byte cache block?
5.1.2 [5] <$5.l> References to which variables exhibit temporal locality?
5.1.3 (5] <$5.l> References to which variables exhibit spatial locality?
Locality is affected by both the reference order and data layout. The same computation
can also be written below in Matlab, which differs from C by storing matrix elements
within the same column contiguously in memory.
for I-1:8
for J-1:8000
A(I,J)-B(1.0)+A(J.I):
end
end
5.1.4 (10] <$5.1> How many 16-byte cache blocks are needed to store all 32-bit
matrix elements being referenced?
5.1.5 [5] <$5.l> References to which variables exhibit temporal locality?
5.1.6 [5] <$5.1> References to which variables exhibit spatial locality?](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F963f6f2d-0bce-4303-b2fb-7d254535557c%2F4371423b-11a7-4250-a849-8d5ffc8d04dd%2F1d40ur_processed.jpeg&w=3840&q=75)
Transcribed Image Text:5.1 In this exercise we look at memory locality properties of matrix computation.
The following code is written in C, where elements within the same row are stored
contiguously. Assume each word is a 32-bit integer.
for (I-0: I<8: I++)
for (J-0: J<8000: J++)
A[IJ[J]-B[I][0]+A[J][1]:
5.1.1 [5) <$5.l> How many 32-bit integers can be stored in a 16-byte cache block?
5.1.2 [5] <$5.l> References to which variables exhibit temporal locality?
5.1.3 (5] <$5.l> References to which variables exhibit spatial locality?
Locality is affected by both the reference order and data layout. The same computation
can also be written below in Matlab, which differs from C by storing matrix elements
within the same column contiguously in memory.
for I-1:8
for J-1:8000
A(I,J)-B(1.0)+A(J.I):
end
end
5.1.4 (10] <$5.1> How many 16-byte cache blocks are needed to store all 32-bit
matrix elements being referenced?
5.1.5 [5] <$5.l> References to which variables exhibit temporal locality?
5.1.6 [5] <$5.1> References to which variables exhibit spatial locality?
![5.3 For a direct-mapped cache design with a 32-bit address, the following bits of the
address are used to access the cache.
Tag
Index
Offset
31-10
9-5
4-0
5.3.1 [5] <$5.3> What is the cache block size (in words)?
5.3.2 [5] <$5.3> How many entries does the cache have?
5.3.3 (5] <$5.3> What is the ratio between total bits required for such a cache
implementation over the data storage bits?
Starting from power on, the following byte-addressed cache references are recorded.
Address
4.
16
132
232
160
1024
30
140
3100
180
2180
5.3.4 (10] <$5.3> How many blocks are replaced?
5.3.5 (10] <$5.3> What is the hit ratio?
5.3.6 [20] <$5.3> List the final state of the cache, with each valid entry represented as
a record of <index, tag, data>.
Microsoft Word
W](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F963f6f2d-0bce-4303-b2fb-7d254535557c%2F4371423b-11a7-4250-a849-8d5ffc8d04dd%2Fqfbshx9_processed.jpeg&w=3840&q=75)
Transcribed Image Text:5.3 For a direct-mapped cache design with a 32-bit address, the following bits of the
address are used to access the cache.
Tag
Index
Offset
31-10
9-5
4-0
5.3.1 [5] <$5.3> What is the cache block size (in words)?
5.3.2 [5] <$5.3> How many entries does the cache have?
5.3.3 (5] <$5.3> What is the ratio between total bits required for such a cache
implementation over the data storage bits?
Starting from power on, the following byte-addressed cache references are recorded.
Address
4.
16
132
232
160
1024
30
140
3100
180
2180
5.3.4 (10] <$5.3> How many blocks are replaced?
5.3.5 (10] <$5.3> What is the hit ratio?
5.3.6 [20] <$5.3> List the final state of the cache, with each valid entry represented as
a record of <index, tag, data>.
Microsoft Word
W
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