DO NOT USE nor, li, etc....ONLY USE RISC-V assembly code (only use instructions from pictures below) RISC-V RV321 Instructions SubsetR-type InstructionsALU performs the required operations on two source registers (rs1 and rs2) and stores ALU result back to thedestination register rd.I-type ALU InstructionsALU performs the required operations on the source register rs1 and immediate constant, and stores the ALU resultback to the destination register rd.CategoryArithmeticLogicalTABLE 3.5 Basic Identities of Boolean AlgebraShiftInstructionAddSubtractAdd immediateSet less thanSet less than immediateSet less than unsignedSet less than immediate, unsignedAndInclusive orExclusive orAnd immediateInclusive or immediateExclusive or immediateShift left logicalShift right logicalShift right arithmeticShift left logical immediateShift right logical immediateShift right arithmetic immediateExampleadd x5, x6, x7sub x5, x6, x7addi x5, x6, 20slt x5, x6, x7slti x5, x6, 20sltu x5, x6, x7sltiu x5, x6, 20and x5, x6, x7or x5, x6, x8xor x5, x6, x9andi x5, x6, 20ori x5, x6, 20xori x5, x6, 20sll x5, x6, x7srl x5, x6, x7sra x5, x6, x7slli x5, x6, 3srli x5, x6, 3srai x5, x6, 3Meaningx5 = x6 +x7x5 = x6 - x7x5 = x6 + 20x5 = x6 3CommentsThree register operands; addThree register operands; subtractUsed to add constantsUsed to compare two registers as 2's complement numbersUsed to compare a register to a constant as 2's complement numbersUsed to compare two registers as unsigned numbersUsed to compare a register to a constant as unsigned numbersThree register operands; bit-by-bit ANDThree register operands; bit-by-bit ORThree register operands; bit-by-bit XORBit-by-bit AND register with constantBit-by-bit OR register with constantBit-by-bit XOE register with constantShift left by registerShift right by registerArithmetic shift right by registerShift left by immediateShift right by immediateArithmetic shift right by immediateData TransferMemory Read (I-type Instructions)Read memory at address (Reg [rsl] + offset) and store to the destination register rd.Memory Write (S-type Instructions)Write register content (Reg [rs2]) to memory at address (Reg [rs1] + offset).CategoryData TransferInstructionluiInstructionExamplelb x5, 40(x6)Ibu x5, 40(x6)Ih x5, 40(x6)Ihu x5, 40(x6)Store byteIw x5, 40(x6)sb x5, 40(x6)sh x5, 40(x6)sw x5, 40(x6)Store halfwordStore wordLoad upper immediatelui x5, 0x12345Add upper immediate to PC auipc x5, 0x12345CategoryLoad byteLoad byte, unsignedLoad halfwordConditionalbranchLoad halfword, unsignedLoad wordU-Type InstructionsLui: load upper immediate instruction which load 20-bit immediate constant from the instruction and storeto the upper 20 bits of the destination register rd.x5, 0xAC516x5= 0xAC516000MeaningInstructionBranch if equalBranch if not equalBranch if less thanBranch if greater orequalBranch if less, unsignedBranch if greater orequal, unsignedUnconditional Jump and linkbranchJump and link registerMeaningx5 = Memory [x6+40]x5 = Memory [x6+40]x5 = Memory [x6 + 40]x5 = Memory [x6+40]x5 = Memory [x6 + 40]Memory[x6 +40] = x5Memory[x6 +40] = x5Memory[x6 + 40] = x5x50x12345000x5 PC + 0x12345000Examplebeq x5, x6, 100bne x5, x6, 100blt x5, x6, 100bge x5, x6, 100Branch Instructions (B-type and J-type)Conditional branch instructions: B-type (if branch condition is true, then go to label; otherwise continue to the nextinstruction after the branch instruction)Unconditional branch instructions: J-type (used for function calls and returns, these two instructions are used as apair.bltu x5, x6, 100bgeu x5, x6, 100Byte from memory to registerUnsigned byte from memory to registerHalfword from memory to registerUnsigned halfword from memory to registerWord from memory to registerByte from register to memoryHalfword from register to memoryWord from register to memoryLoads 20-it constant shifted left 12 bitsUsed for PC-relative data addressingjal x1, 100jalr x1, 100 (x5)CommentsU-Type Format001011010 1100 0101 0001 0110Meaningif (x5 x6) go to PC+100if (x5 x6) go to PC+100if (x5 x6) go to PC+100if (x5 x6) go to PC+100if (x5 x6) go to PC+100if (x5 x6) go to PC+100x1 = PC+4; go to PC+100x1 = PC+4; go to x5+1000110111CommentsPC-relative branch if registers equalPC-relative branch if registers not equalPC-relative branch if registers lessPC-relative branch if registers greateror equalPC-relative branch if registers less,unsignedPC-relative branch if registers greateror equal, unsignedPC-relative procedure callProcedure return; indirect call 5.Convert the following high-level code into RISC-V assembly language. Assumethat the signed integer variables g and ŉ are in registers to and t1, respectively. You canuse other temporary registers like t2 and t3 if needed.a)b)if (g % 8 == 3 || g % 8 == 5)h = h * 5.5;elseh = h 16;if (g % 16 4 && g % 16

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DO NOT USE nor, li, etc....ONLY USE RISC-V assembly code (only use instructions from pictures below) RISC-V RV321 Instructions SubsetR-type InstructionsALU performs the required operations on two source registers (rs1 and rs2) and stores ALU result back to thedestination register rd.I-type ALU InstructionsALU performs the required operations on the source register rs1 and immediate constant, and stores the ALU resultback to the destination register rd.CategoryArithmeticLogicalTABLE 3.5 Basic Identities of Boolean AlgebraShiftInstructionAddSubtractAdd immediateSet less thanSet less than immediateSet less than unsignedSet less than immediate, unsignedAndInclusive orExclusive orAnd immediateInclusive or immediateExclusive or immediateShift left logicalShift right logicalShift right arithmeticShift left logical immediateShift right logical immediateShift right arithmetic immediateExampleadd x5, x6, x7sub x5, x6, x7addi x5, x6, 20slt x5, x6, x7slti x5, x6, 20sltu x5, x6, x7sltiu x5, x6, 20and x5, x6, x7or x5, x6, x8xor x5, x6, x9andi x5, x6, 20ori x5, x6, 20xori x5, x6, 20sll x5, x6, x7srl x5, x6, x7sra x5, x6, x7slli x5, x6, 3srli x5, x6, 3srai x5, x6, 3Meaningx5 = x6 +x7x5 = x6 - x7x5 = x6 + 20x5 = x6 < x7x5 = x6 < 20x5 = x6 <₁ x7x5 = x6 <₁ 20x5 = x6 & x7x5 = x6 | x8x5 = x6 ^ x9x5 = x6 & 20x5 = x6 | 20x5 = x6 ^ 20x5 = x6 << x7x5 = x6 >> x7x5 = x6 >> x7x5 = x6 << 3x5 = x6 >> 3x5 = x6 >> 3CommentsThree register operands; addThree register operands; subtractUsed to add constantsUsed to compare two registers as 2's complement numbersUsed to compare a register to a constant as 2's complement numbersUsed to compare two registers as unsigned numbersUsed to compare a register to a constant as unsigned numbersThree register operands; bit-by-bit ANDThree register operands; bit-by-bit ORThree register operands; bit-by-bit XORBit-by-bit AND register with constantBit-by-bit OR register with constantBit-by-bit XOE register with constantShift left by registerShift right by registerArithmetic shift right by registerShift left by immediateShift right by immediateArithmetic shift right by immediateData TransferMemory Read (I-type Instructions)Read memory at address (Reg [rsl] + offset) and store to the destination register rd.Memory Write (S-type Instructions)Write register content (Reg [rs2]) to memory at address (Reg [rs1] + offset).CategoryData TransferInstructionluiInstructionExamplelb x5, 40(x6)Ibu x5, 40(x6)Ih x5, 40(x6)Ihu x5, 40(x6)Store byteIw x5, 40(x6)sb x5, 40(x6)sh x5, 40(x6)sw x5, 40(x6)Store halfwordStore wordLoad upper immediatelui x5, 0x12345Add upper immediate to PC auipc x5, 0x12345CategoryLoad byteLoad byte, unsignedLoad halfwordConditionalbranchLoad halfword, unsignedLoad wordU-Type InstructionsLui: load upper immediate instruction which load 20-bit immediate constant from the instruction and storeto the upper 20 bits of the destination register rd.x5, 0xAC516x5= 0xAC516000MeaningInstructionBranch if equalBranch if not equalBranch if less thanBranch if greater orequalBranch if less, unsignedBranch if greater orequal, unsignedUnconditional Jump and linkbranchJump and link registerMeaningx5 = Memory [x6+40]x5 = Memory [x6+40]x5 = Memory [x6 + 40]x5 = Memory [x6+40]x5 = Memory [x6 + 40]Memory[x6 +40] = x5Memory[x6 +40] = x5Memory[x6 + 40] = x5x50x12345000x5 PC + 0x12345000Examplebeq x5, x6, 100bne x5, x6, 100blt x5, x6, 100bge x5, x6, 100Branch Instructions (B-type and J-type)Conditional branch instructions: B-type (if branch condition is true, then go to label; otherwise continue to the nextinstruction after the branch instruction)Unconditional branch instructions: J-type (used for function calls and returns, these two instructions are used as apair.bltu x5, x6, 100bgeu x5, x6, 100Byte from memory to registerUnsigned byte from memory to registerHalfword from memory to registerUnsigned halfword from memory to registerWord from memory to registerByte from register to memoryHalfword from register to memoryWord from register to memoryLoads 20-it constant shifted left 12 bitsUsed for PC-relative data addressingjal x1, 100jalr x1, 100 (x5)CommentsU-Type Format001011010 1100 0101 0001 0110Meaningif (x5 x6) go to PC+100if (x5 x6) go to PC+100if (x5 x6) go to PC+100if (x5 > x6) go to PC+100if (x5 x6) go to PC+100if (x5 > x6) go to PC+100x1 = PC+4; go to PC+100x1 = PC+4; go to x5+1000110111CommentsPC-relative branch if registers equalPC-relative branch if registers not equalPC-relative branch if registers lessPC-relative branch if registers greateror equalPC-relative branch if registers less,unsignedPC-relative branch if registers greateror equal, unsignedPC-relative procedure callProcedure return; indirect call 5.Convert the following high-level code into RISC-V assembly language. Assumethat the signed integer variables g and ŉ are in registers to and t1, respectively. You canuse other temporary registers like t2 and t3 if needed.a)b)if (g % 8 == 3 || g % 8 == 5)h = h * 5.5;elseh = h 16;if (g % 16 > 4 && g % 16 < 12)h = (g + 5 * h) % 8;elseh = (g + 8.5 * h)* 9;

Accepted Answer

5. a) Answer : Assuming that the initial values of g and h are already stored in registers t0 and t1…