4. A PN flip-flop has four operations: set to 1, complement, no change and clear to 0, when inputs P and N are 00, 01, 10, and 11, respectively. (a) Tabulate the characteristic table. (b) Tabulate the excitation table. (c) Show how the PN flip-flop can be converted to a T flip-flop

Electric Motor Control
10th Edition
ISBN:9781133702818
Author:Herman
Publisher:Herman
Chapter22: Sequence Control
Section: Chapter Questions
Problem 6SQ: Draw a symbol for a solid-state logic element AND.
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Please answer fourth question from digital electronics asap
3b
Q.
Q Q,
D.
4. A PN flip-flop has four operations: set to 1, complement, no change and clear to 0, when
inputs P and N are 00, 01, 10, and 11, respectively.
4
(a) Tabulate the characteristic table. (b) Tabulate the excitation table. (c) Show how the PN
flip-flop can be converted to a T flip-flop
5. Design 3 bit: Synchronous Down counter with D flipflops.
6. (a) Design PLA for the following Boolean functions (A, B. C)-E(0, 2, 3, 4,7) and
(5 M)
A(A. B. C) - 1, 5. 6. 7).
(5 M)
(b) Design CMOS circuit for the Boolean function Y= A+ (B-C)D.
Transcribed Image Text:3b Q. Q Q, D. 4. A PN flip-flop has four operations: set to 1, complement, no change and clear to 0, when inputs P and N are 00, 01, 10, and 11, respectively. 4 (a) Tabulate the characteristic table. (b) Tabulate the excitation table. (c) Show how the PN flip-flop can be converted to a T flip-flop 5. Design 3 bit: Synchronous Down counter with D flipflops. 6. (a) Design PLA for the following Boolean functions (A, B. C)-E(0, 2, 3, 4,7) and (5 M) A(A. B. C) - 1, 5. 6. 7). (5 M) (b) Design CMOS circuit for the Boolean function Y= A+ (B-C)D.
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