3.36 Draw the logic diagram of the digital circuit specified by the following Verilog description: (a) module Circuit_A (A, B, C, D, F); input output wire А, В, С, D; F; W, X, y, z, a, d; (х, В, С, d); (у, а ,С); (w, z ,B); (z, y, A); (F, x, w); (а, А); (d, D); or and > and and or not not endmodule (b) module Circuit_B (F1, F2, F3, A0, A1, B0, B1); output input F1, F2, F3; A0, A1, B0, B1; (F1, F2, F3); (F2, w1, w2, w3); (F3, w4, w5); (w1, w6, B1); (w2, w6, w7, B0); (w3, w7, B0, B1); (w6, A1); (w7, A0); (w4, A1, B1); (w5, A0, BO); nor or and and or and not not xor xnor endmodule (c) module Circuit_C (y1, y2, y3, a, b); output y1, y2, y3; input a, b; assign y1 = a || b; and (y2, a, b); assign y3 = a && b; endmodule

3.36 Draw the logic diagram of the digital circuit specified by the following Verilog description: (a) module Circuit_A (A, B, C, D, F); input output wire А, В, С, D; F; W, X, y, z, a, d; (х, В, С, d); (у, а ,С); (w, z ,B); (z, y, A); (F, x, w); (а, А); (d, D); or and > and and or not not endmodule (b) module Circuit_B (F1, F2, F3, A0, A1, B0, B1); output input F1, F2, F3; A0, A1, B0, B1; (F1, F2, F3); (F2, w1, w2, w3); (F3, w4, w5); (w1, w6, B1); (w2, w6, w7, B0); (w3, w7, B0, B1); (w6, A1); (w7, A0); (w4, A1, B1); (w5, A0, BO); nor or and and or and not not xor xnor endmodule (c) module Circuit_C (y1, y2, y3, a, b); output y1, y2, y3; input a, b; assign y1 = a || b; and (y2, a, b); assign y3 = a && b; endmodule

Introductory Circuit Analysis (13th Edition)

13th Edition

ISBN:9780133923605

Author:Robert L. Boylestad

Publisher:Robert L. Boylestad

Chapter1: Introduction

Section: Chapter Questions

Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...

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