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- With the following functions use a 4:1 multiplexer(mux) and minimum number of extra gates. Remember that to create the inverse of an input variable (i.e., A’, B’, etc.), you need to use an inverter. Hint:remember that you may need to try different variables on the select lines (i.e., A and B, or B and C, or A and C) to find the solution with the minimum number of extra gates. Implement each of the functions from from the above question using a 2:1 multiplexer(mux) and a minimumnumber of extra gates. Hint:remember that you may need to try different variables (i.e., A or B or C) on the select line to find the solutionwith the minimum number of extra gates. please explain in detail with a truth table as well as the schematics using a MUX.Disscussion 1- In OR gate table why 1+ 1 = 1? 2- Explain the basic logic gates, complete three and four input logic gates truth table.. 3- What is the purpose of a truth table and algebraic function? 4-What is the purpose of an inverter in a digital circuit? -5- When is the output of an OR gate HIGH? -6- When is the output of an OR gate LOW? 7- Describe the truth table for a 3-input OR gate.Sometimes "bubbles" are used to indicate inverters on the input lines to a gate. What are the equivalent gates for those shown in the figure below? Hint - use DeMorgan's Law. A B C=A+B (a) D F=DE E (b)
- Consider a family of logic gates that operate under the static discipline with the following voltage thresholds: VI=1.5V, VOL=0.5V, VIH=3.5V, and VOH=4.4V. a. What is the lowest voltage that can be output by an inverter for a logical 1 output? Why? b. What is the highest voltage that must be interpreted by a receiver as logical 0? Why? c. What is the lowest voltage that must be interpreted by a receiver as logical 1? Why?6. F in the blanks in the truth table of the given digital circuit NOT Use fer NOT gate egX. Use paranthesis only for combining two logic gates OR and AND e ZOX+Y) er (Y+Z).OX+Y) You can use either XY or X.Y for AND gate. Write the letters in alphabetic orders: eg XY, not YX 1 5Logic Gates:* 7404LS (NOT)* 7408LS (AND)* 7432LS (OR)* 7400LS (NAND)* 7402LS (NOR)* 7486LS (EX-OR)Or you can use 74HCxx versions. Task 2: 4 INPUT PRIORITY ENCODERa) Write the truth table.b) Find the outputs in terms of min terms using minimal expression.c) By using K map, find the simple/simplest expression of theoutputs.d) Draw the circuit diagram. (Simulation design will be accepted.)e) Simulate the circuit & explain your results. (Please do notdesign separate simulations for each output. You should design ONEsimulation including all inputs and outputs.)
- Consider a family of logic gates that operate under the static discipline with the following voltage thresholds: VI=1.5V, VOL=0.5V, VIH=3.5V, and VOH=4.4V. a. What is the lowest voltage that can be output by an inverter for a logical 1 output? Explain. b. What is the highest voltage that must be interpreted by a receiver as logical 0? Explain. c. What is the lowest voltage that must be interpreted by a receiver as logical 1? Explain.parity generator design, construct and test a circuit that generates an even parity bit ffrom four messages bits . use XOR gates. adding one more XOR gate, expand the circuit so that it generates an odd parity bit also.Exclusive OR (XOR) and Exclusive NOR (XNOR) gates can be used a. as parity generators b. as parity checkers c. as comparators d. as controlled inverters e. as all of the given answers
- ehcu.org/pluginfile 100% 10 / 11 locations, count how many times is 0 and how many times 1 is. Questions:- 1- Write a program in assembly language to perform the following logic ci BL CL DL [5100]- 2- How we can perform the NEG and NOT instructions by using different instructions. 3- Write the following program by using different instruction or instructions for each instruction on the program. MOV AL , 00 MOV BX , FFFF XOR CL , FF NEG BYTE PTR [DI] AND CX , LGProblem #04] Using AND and OR gates develop the logic circuit for the Boolean equation shown below. Y =AB(C + DEF) + CE(A + B +F) Problem #05] Using AND and OR gates develop the logic circuit for the Boolean equation shown below. X-A(CD+B)3. Logic Design a. Create the truth table of a 3-input AND gate. Realize the 3-input AND operation using only 2-input NOR gates. b. Create the truth table of a 3-input OR gate. Realize the 3-input OR operation using only 2- input NAND gates. c. Using AND and OR logic gates, implement the logic function: F(x, y, z) = xy + yz + zx d. Using NAND logic gates, implement the logic function: F(x, y, z) = xy + yz + zx