3. For the following sequence of instructions, assume that it is executed on a 5-stage pipelined datapath. If there is no forwarding or hazard detection, insert nops to ensure correct execution and explain why need to elaborate on how you get your answer. Without proper explanations, you will lose points.) add St5, St2, St1 Iw St3, 4 (St5) Iw St2, 0(St2) or St3, St5, St3 sw St3, 0(St5)

3. For the following sequence of instructions, assume that it is executed on a 5-stage pipelined datapath. If there is no forwarding or hazard detection, insert nops to ensure correct execution and explain why need to elaborate on how you get your answer. Without proper explanations, you will lose points.) add St5, St2, St1 Iw St3, 4 (St5) Iw St2, 0(St2) or St3, St5, St3 sw St3, 0(St5)

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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[ Direction: Any how solve the question please. Don't reject the question. if you need 2 /3 hours to solve the question please take it but don't reject the question. solve it properly,correctly.You can consult any resources such as books, online references, and videos for this assignment, however, you have to properly cite and paraphrase your answers when it is necessary. ] The following figure represents both datapath and controlpath for MIPS architecture that implements most of the fundamental instrucons.
7. In a normal branch instruction, we provide the number of instructions we need to go to with respect to the current Program Counter. We want to modify this in the datapath. Suppose, instead of providing the number of instructions, we provide it 16-bit address, which when sign extended to 32 bits and then add 8 to it, will provide the exact address to branch to, what modifications will you make in the datapath below to accommodate it.
6. Suppose that the interrupt processing method of is to store the breakpoint in the address of 00000Q unit, and fetch the instruction from the 77777Q unit (that is the first instruction of the interrupt service routine) and execute it. Write the micro-operations sequence that completes this function.
Lab work 1: Assume you want to execute the instruction SW (store word) on the MIPS single-cycle data path. Draw the relevant datapath components and lines for the SW instruction (use slide 31 of week10 lecture as a reference). Just include the required components and control lines for this instruction. For example: sw $t2, 5($t1).
The instruction “addi” is an I-type instruction that can be executed using the Single-cycle datapath without modification. Answer the following question: (a) Give values of all control signals needed to execute this instruction on the single-cycle data. For example: addi $t2, $S2, 3.
2. Assume following sequence of instructions. Assume R-type, LW, Sw, branch, arithmetic immediate and jump instructions take 6, 8, 6, 7, 5 and 7 ns respectively. What will be the total execution time if you are running those instructions into a single-cycle datapath design? Draw flow/path of executions. SUB $s0, Șto, Șt1 LW $1, 40($s3) ADD $s2, $t2, $to ADDI $4, St3, 175 BNE $5, $56, 1 sw $s1, 44($s3) J 1000 In multi-stage pipeline (MIPS) if the stages take 2, 1, 2, 2, 1 ns respectively, what will be the total execution time for above code statements/generated instructions? Draw flow/path of executions. (assume forwarding is not implemented)
Building a Datapath [1.1] Consider the following instruction: Instruction: Interpretation: Reg[rd] Reg[rs1] AND Reg[rs2] a. What are the values of control signals generated by the control in the Figure below for this instruction? b. Which resources (blocks) perform a useful function for this instruction? c. Which resources (blocks) produce no output for this instruction? Which resources produce output that is not used? Instruction Read register 1 Read register 2 Registers Read data 2 Write register Write data RegWrite Read data 1 a. or rd, rs1, rs2 b. sub rd, rsl, rs2 c. lw rd, offset (rs1) Imm Gen ALUSrc ALU operation Zero ALU ALU result Address Write data MemWrite Read data Data memory MemtoReg MemRead
What is the main issue of a single data path design? Need multiple Multiplexors. Longest delay determines clock period. Does not support JUMP instruction. Each datapath element can only do one function at a time.
Consider each of the following cases, and determine when the instruction's bytes are "complete" (all bytes are specified and do not need to be changed further). Answer the following with "at assembly time," "at linkage time," or "at runtime." a. lea rax, [abs msg] ; msg is a location in the same section b. lea ax, [zel msg) ; msg is a location in the same section C. lea rax, [xel msg] ; msg is a location in a different section of your program d. lea rax, [ errno location] errno location is in a statically-linked library е. lea rax, I errno location] errno location is in a dynamically-linked library
In an instruction cycle the execute phase includes Select one: a.the operation of the decoded instruction on all the operands. b.there is no correct answer here c.incrementing the program counter by 2 addresses. d.the step of decoding the instruction for execution. e.the transfer of the content of memory address pointed by the program counter.
(b) Read each sentence of this question carefully. You may agree/disagree with each sentence (treat each sentence independently) with proper reason (not in more than 2 lines for each sentence). “Daisy chaining scheme may cause starvation”. “In DMA transfer, the received data is stored at contiguous memory locations”. “Multiple interrupt line is the most difficult way of device identification”. “CPU requires more time to handle an interrupt request than a DMA request”. “InfiniBand operation has a layered approach architecture”.
[ Direction: Any how solve the question please. Don't reject the question. if you need 2 /3 hours to solve the question please take it but don't reject the question. solve it properly,correctly.You can consult any resources such as books, online references, and videosfor this assignment, however, you have to properly cite and paraphrase your answerswhen it is necessary. ] The following figure represents both datapathand controlpath for MIPS architecture that implements most of thefundamental instrucons.