21. Suppose we have 2 bytes of virtual memory and 2° bytes of physical main memory. Suppose the page size is 24 bytes. 1. a) How many pages are there in virtual memory? 2. b) How many page frames are there in main memory? 3. c) How many entries are in the page table for a process that uses all of virtual memory?

21. Suppose we have 2 bytes of virtual memory and 2° bytes of physical main memory. Suppose the page size is 24 bytes. 1. a) How many pages are there in virtual memory? 2. b) How many page frames are there in main memory? 3. c) How many entries are in the page table for a process that uses all of virtual memory?

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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8.14. In the S/370 architecture, a storage key is a control field associated with each page- sized frame of real memory. Two bits of that key that are relevant for page replace- ment are the reference bit and the change bit. The reference bit is set to 1 when any address within the frame is accessed for read or write, and is set to 0 when a new page is loaded into the frame. The change bit is set to 1 when a write operation is per- formed on any location within the frame. Suggest an approach for determining which page frames are least-recently-used, making use of only the reference bit.
Q.2 Suppose a system has a logical address space of size 25 (m=5), a page size of 4 bytes, and a physical memory of 128 bytes. Given the following page table, find out the respective physical addresses for each of the logical address listed in Table 2. (Note: all addresses are expressed in decimal number system) Table 1: Page table 0 2 5 7 0 15 1 2 3 4 5 18 6 20 7 22 Table 2: Fill out this table with corresponding physical memory addresses Logical Address Physical Address 0 6 10 17 23
Exercise 2: A byte addressable memory has a size of 1024 MBytes. This memory is attached to a direct mapping cache of 32KBytes that contains 1024 lines. a. What is the memory address length? b. What is the block size? c. What is the number of blocks in main memory? d. What is the length in bit of: tag (T), line number (L) and byte number (W)? e. Determine in Hexadecimal the tag (T), line number (L) and byte number (W) of the following Hexadecimal memory address: 000008AE f. What is the block that contains the address 000000DE? g. Which line of the cache can hold the block containing 000000DE?
Consider a program consists of five segments: S0 = 600, S1 = 14 KB, S2= 100 KB, S3 =580 KB and S4 = 96 KB. Assume at that time, the available free space partitions of memory are 1200–1805, 50 – 150, 220-234, and 2500-3180.Find the following:d. What are the addresses in physical memory for the following logical addresses: 0.580, (b) 1.17 (c) 2.66 (d) 3.82 (e) 4.20?
Main memory size is 16 pages. Size of swap file on hard disk is 64 pages. Operating system locks down pages 0, 1, 2 and 7 in the main memory. Two programs are started and both are provided with a virtual address space of 10 pages. Initially operating system allocates 5 pages of main memory for each program and the rest from swap file. Virtual address space of each program starts from page 0. Construct page tables for both programs at program startup. A page table consists of P-bit which tells if the page is present in the main memory (1 = page is in main memory) and address of the page. Address tells either real address in main memory or the address of the page in swap file. b. A computer with a paged virtual memory system executes two load instructions that are adjacent to each other in memory. Describe the worst case scenario (in terms of performance) that can occur during the execution of the two instructions and explain under which conditions this case occurs. How does this affect…
a) A process references five pages, A, B, C, D, and E, in the following order: A; B; C; D; A; B; E; A; B; C; D; E Assume that the replacement algorithm is first-in-first-out (FIFO) and find the number of page transfers during this sequence of references starting with an empty main memory with three-page frames.
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Q: A digital computer has a memory unit of 64k * 16 and a cache memory of 1k words. The cache uses direct mapping with a block size of 4 words. i) How many bits are there in the tag, index, block & words fields of the address formats. ii) How many bits are there in each word of cache? iii) How many blocks can the cache accommodate?
Giventhe following assignment of some program’s virtual pages to physical pages in a system with 4 KiB byte pages, what physical memory address corresponds to virtual address 20000? (All values are given in decimal.)
A computer of 32 bits has a cache memory of 64 KB with a cache line size of 64 bytes. The cache access time is 20 ns, and the miss penalty is 120 ns. The cache is 2-way associative. a) What is the number of cache lines? b) What is the number of cache sets? c) What is the number of lines per set? d) Draw a scheme of this cache. e) Calculate the time to read a word in case of miss.
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Following is a mapping of Logical Memory to Physical Memory using a Page Table. You are required to fill the Page Table: Physical Memory 1 Page 5 Logical Memory Page 0 2 Page 2 Page 1 3 Page 4 Page 2 4 Page 3 5 Page 0 Page 4 6 7 Page 1 8 Page 3 Page 5 Page Table 1 3.