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- Please solve this problem in emu8086 microprocessor in Assembly Language. Please solve properly, will upvote after getting proper solve Read 10 inputs (range 0-9) from the user and store them in an array. Find the position (or index) of the maximum and minimum values in the array, and swap them (move the biggest element to the position of the smallest, and move the smallest element to the position of the biggest), and print that again. If there are multiple maximum or minimum numbers, then choose the first occurrence, values. Your program should be able to handle negative values. Explanation: Here from the given input we see that 9 is the maximum number and it has occurred twice, first in the 2nd index and again in the 5th index. Similarly here 3 is the least and it also has appeared twice, once in the 3rd index and again in the 6th index. So we swap 9 and 3 from the 2nd and 3rd indices and then after swapping, print the new array. Input: 7935935874 Output: 7395645874 Comment:Range 0…6. What is the address of executing the following instruction: MOV CX, [FEH] if you know that DS= DC00H? OCL: DCOFEH, CH: DCOFFH OCL: DCFEH, CH: DCFFH CL: DCFFH, CH: DCFFH CL: DCOFFH, CH: DCOFFHQuiz 5: In this problem we want to set the control signals of the datapath shown below (also in in slide # 1 of "chapter3_single_cycle_datapaths.pptx") so that it supports execution of a new instruction called swi. Single Cycle Datapath: PC Read Instru- address ction [31-0] Instruction memory Sns Add Ins 1 [25-21] 1 [20-16] [15-11]. 1[10-0] RegWrite Read register 1 Read register 2 Write register Write data Read data 1 Read data 2 Read Ins Write 3ns Sign extend 2ns MemWrite Read Read address data Write address Read Gns Write data Write 10ns ins ALUSTO1 MemRead ALU Result 2ns ALUOP1 -XEWO) ins ALUSrc2 ALUSrc3 x=3 ins ALU Result 2ns ALUOP2 swi rd, rs, rt, imm # Memory [R[rs]]= R[rt], R[rd] =R [rs]+R [rt]+Imm #this instruction copies contents of "rt" register into the main memory addressed by the "rs" register. In the same cycle it add "rs" and "rt" register contents along with the "imm" field of the instruction and writes the final result into the "rd" register. You are NOT allowed to…
- The 32-bit RISC-V base integer instruction set (rv32i) does not support multiplication and division operations. To deal with this, a compiler may call a function when a multiplication is needed. For example, gcc expects that a function - mulsi3(unsigned int a, unsigned int b) is provided to multiply two integers. A multiplication can be carried out by repeated additions and shifts: unsigned int -_mulsi3 (unsigned int a, unsigned int b) { unsigned int r = 0; while (a) { if (a & 1) { r += b; } a >>= 1; b <<= 1; } return r; } a) Translate the above C code into equivalent RISC-V rv32i assembler code. Comment the as- sembler code to explain how the calculation proceeds. Note that the arguments are passed via the registers a0 (x10) and a1 (x11) and that the result is returned in a0 (x10). b) Does the function need function call prolog and epilog? Explain why or why not. You are invited to use emulsiV to develop and test your assembler code.Consider each of the following cases, and determine when the instruction's bytes are "complete" (all bytes are specified and do not need to be changed further). Answer the following with "at assembly time," "at linkage time," or "at runtime." a. lea rax, [abs msg] ; msg is a location in the same section b. lea ax, [zel msg) ; msg is a location in the same section C. lea rax, [xel msg] ; msg is a location in a different section of your program d. lea rax, [ errno location] errno location is in a statically-linked library е. lea rax, I errno location] errno location is in a dynamically-linked libraryTake the following machine language instruction and fill in the translation of it in assembly language. The "alternative operand values" is how the operand may be expressed in assembly language either has hex (prefixed with Ox) or decimal (not prefixed with Ox). C00005 Binary IS: Mask: Instruction: [Select] [Select] [Select] [Select] Operand specifier: (four hex digits) Operand specifier: [Select] (alternative operand values) Addressing mode: [Select] (symbolic) Assembly: [Select] (instruction and operand)
- Q5. Array A contains 128 entries, each of which is a 32-bit integer. The address of A[0] is stored in Register#3 (R[3]). How do you move A[55] into Register#4 (R[4])?There is an application that requires the following hardware: an Intel 8031, a Program ROM of 8Kx8, a Data ROM of 4Kx8 for look-up tables and a Data RAMs of 8Kx8. The memory map of the design: Program ROM should start at address 0000H. Then, the Data ROM should come above the Program ROM. Finally the Data RAM must go to the top of the memory map. There should be no gaps between the memory addresses of the external ROMs. Calculate the address space of the ROMs and RAMs of your design.There is an application that requires the following hardware: an Intel 8031, a Program ROM of 8Kx8, a Data ROM of 4Kx8 for look-up tables and a Data RAMs of 8Kx8. The memory map of the design: Program ROM should start at address 0000H. Then, the Data ROM should come above the Program ROM. Finally the Data RAM must go to the top of the memory map. There should be no gaps between the memory addresses of the external ROMs. Show the design’s address space on a memory map, starting with 0000H at the bottom and FFFFH at the top.
- Write MIPS code to calculate Arr[i+3] = Arr[i] (this is an assignment statement that transfers the word in Arr[i] to Arr[i+3]). Assume Arr and i are already defined in memory. In your code, the base address of array Arr and index i must be loaded into registers $s0 and $s1 respectively.Assume that you have a A= 5x5 Matrix with one byte size elements.. Write an Assembly program that places its transpose A' just after A in 8086 physical memory and also places transpose of transpose (A) just after A' . The basic mechanism must use SI and DI registers.The whole codes must work, otherwise no points. WHEN YOU FINISHED THIS QUESTION ONLY, YOU HAVE TO SEND THE COPY OF THIS CODE to YOUR INSTRUCTOR as a TXT or WORD FILE THRU STIX AFTER EXAM ( IF YOU ARE SURE THE CODES ARE WORKING FINE!! OTHERWISE DON'T SEND !)5. Below is a depiction of a loop in instruction memory address Охо TOP: instruction 1 Ox4 instruction 2 Ox8 instruction 3 OxC instruction 4 Ох10 conditional branch to TOP Assume that the branch target buffer is initially empty, and the prediction bits are set to Strongly Taken (ST). Fill in the blanks On the first pass through the loop we take the branch. The branch target bits are now We suffer stalls. On the second pass through the loop we don't take the branch. The branch target bits are now We suffer stalls. On the third pass through the loop we don't take the branch. The branch target bits are now We suffer stalls. On the fourth pass through the loop we don't take the branch. The branch target bits are now We suffer stalls.