1. What is the primary problem when dealing with branches (such as beq and bne in ARM) in pipeline designs? You need to fetch an instruction after the branch before knowing the branch outcome Calculating if the branch should be taken or not taken complicates the design of the Execute (or ALU) stage You can have a branch dependent on a value loaded from memory which delays completing the branch Branches pose no more problem than any non-branch instruction for a pipeline

1. What is the primary problem when dealing with branches (such as beq and bne in ARM) in pipeline designs? You need to fetch an instruction after the branch before knowing the branch outcome Calculating if the branch should be taken or not taken complicates the design of the Execute (or ALU) stage You can have a branch dependent on a value loaded from memory which delays completing the branch Branches pose no more problem than any non-branch instruction for a pipeline

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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In a perfectly balanced pipelined implementation, the time required to execute each individual instruction is same as for non-pipelined implementation. Select one: O True O False
In an unbalanced pipelined implementation, the time required to execute each individual instruction is same as for non-pipelined implementation. Select one: O True O False
Orthogonality is the property of an instruction set design to have a "backup" instruction for every other instruction that accomplishes the same purpose as the original instruction. You are free to enlighten me as to whether or not it is true.
5. Pipelined datapath has five stages, ie., instruction fetch (IF), decode (ID), execution (EX), memory (MEM), and write back (WB). It has a hazard detection unit. An instruction will be stalled at the decode stage if any of its operands isn't ready. Consider executing the following code on this datapath (1) At the end of fifth cycle of execution, what instruction will be in each of the pipeline stages? (If there is any "bubble" in the pipeline, please write "NOP" in the corresponding pipeline stage.) (5%) You must write the answer with the following format. instruction IF instruction lw $r2, 10($1) sub $r4, $13, Sr2 add $r5, Sr6, $7 and Sr8, Sr4,$r5 IF ID EX (2) If the datapath has a forwarding unit to resolve the data hazard, what instruction will be in each of the pipeline stages at the end of the fifth cycle? (If there is any "bubble" in the -pipeline, please write "NOP" in the corresponding pipeline stage.) (5%) You must write the answer with the following format: (D MEM EX WB.…
If the execution time of pipeline instruction execution is not balanced, what inefficiency must be introduced to allow the piplelined execution to occur? Describe this inefficiency.
Orthogonality occurs when an instruction set design includes a "backup" instruction for any other instruction that accomplishes the same task. You may tell me whether or not it is correct.
use: Microchip Studio and ATmega328p Activity 2: SUB instruction flags Write and assemble the following program. SUB instruction can trigger Z(Zero), C(Carry), N(Negative), V(Overflow), and H(Half Carry) flags. Use the simulator to single- step and examine the flags and register content after the execution of each flag triggering instruction. LDI R20, $27 LDI R21, $15 SUB R20, R21 LDI LDI SUB R20, $20 R21, $15 R20, R21 R24,95 R25,95 LDI LDI SUB R24, R25 LDI R22,50 LDI R23, 70 SUB R22, R23 End: RJMP End R20- → R20 = → R24 = ➜ R22= [Hex], Active Flags: [Hex], Active Flags: [Hex], Active Flags: [Hex], Active Flags:
Write HCL code for the signal D_stall in the PIPE implementation.Pipeline register D must be set to bubble for a mispredicted branch ora ret instruction. As the analysis in the preceding section shows,however, it should not inject a bubble when there is a load/use hazardin combination with a ret instruction:bool D_bubble =# Mispredicted branch (E_icode == IJXX && !e_Cnd) ||# Stalling at fetch while ret passes through pipeline# but not condition for a load/use hazard!(E_icode in { IMRMOVQ, IPOPQ } && E_dstM in { d_srcA,d_srcB }) && IRET in { D_icode, E_icode, M_icode };
please do not copy and paste another online answer Provide answer with a valid reason 1) A special type of problem occurs with a Branch instruction, since the processorcannot immediately determine whether or not the branch will be taken. The nextinstruction will be fetched before the determination is made. In this case, if thebranch is taken, then the following instruction would not be executed, and the mostrecently fetched instruction must be discarded, and replaced by the branch target.Possible solutions to this problem are ______ and _________. a) Bypassing with additional hardware; Predicting the Branch decision before it is actuallymade.b) Stall pipeline until determination is made; Predicting the Branch decision before it is actually made.c) Stall pipeline until determination is made; Bypassing with additional hardware.d) Bypassing with additional hardware; A Branch instruction mus always be followed by a NOP.
A PC-relative mode branch instruction is 4 bytes long. The address of the instruction is 0x00000123 in hex form. Determine the branch target address in decimal form if the signed displacement in the instruction is 0xFFFFFFAB in hex form. Note: PC always has the address of the next instruction. Please don't ask me for free upvote. I will not provide upvote is there is no answer or wrong answer. Thanks.
Is it possible to achieve piplelined execution if the execution time of pipeline instruction execution is not balanced? What inefficiency do you see here?
Q7. For the following loop, assume the loop executes many iterations (the branch is almost always taken). What would be the steady state CPI of this code (e.g., assume branch always taken)? Assume the 5-stage MIPS pipeline, no branch delay slot in the ISA, branches resolved in the ID stage, and "predict branch not taken" strategy with one instruction squashed on a mispredict. loop: add R4, R6, R8 subi R2, R2, #8 lw R8, 1000 (R4) add R9, R8, R7 bne R2, R4, loop