1.) The source register values are as follows: $s1 0000 0000 0000 0000 0000 0000 0000 1101 $s2 0100 0110 1010 0001 1111 0000 1011 0111 a.) What is the result of $t0, after executing the following: sll $t0, $s1, 4 $s1 0000 0000 0000 0000 0000 0000 0000 1101 $t0 b.) What is the result of $t1, after executing the following:
1.) The source register values are as follows:
$s1 |
0000 |
0000 |
0000 |
0000 |
0000 |
0000 |
0000 |
1101 |
$s2 |
0100 |
0110 |
1010 |
0001 |
1111 |
0000 |
1011 |
0111 |
a.) What is the result of $t0, after executing the following:
sll $t0, $s1, 4
$s1 |
0000 |
0000 |
0000 |
0000 |
0000 |
0000 |
0000 |
1101 |
$t0 |
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b.) What is the result of $t1, after executing the following:
srl $t1, $s1, 4
$s1 |
0000 |
0000 |
0000 |
0000 |
0000 |
0000 |
0000 |
1101 |
$t1 |
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c.) What is the result of $t2, after executing the following:
nor $t2, $s2, $zero
$s2 |
0100 |
0110 |
1010 |
0001 |
1111 |
0000 |
1011 |
0111 |
$zero |
0000 |
0000 |
0000 |
0000 |
0000 |
0000 |
0000 |
0000 |
$t2 |
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d.) What is the result of $t3, after executing the following:
AND $t3, $s1, $s2
$s1 |
0000 |
0000 |
0000 |
0000 |
0000 |
0000 |
0000 |
1101 |
$s2 |
0100 |
0110 |
1010 |
0001 |
1111 |
0000 |
1011 |
0111 |
$t3 |
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e.) What is the result of $t4, after executing the following:
OR $t4, $s1, $s2
$s1 |
0000 |
0000 |
0000 |
0000 |
0000 |
0000 |
0000 |
1101 |
$s2 |
0100 |
0110 |
1010 |
0001 |
1111 |
0000 |
1011 |
0111 |
$t4 |
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