1. Consider the following MIPS assembly language code: H: LW Se0, 4(S1) 12: ADD Se1, S0, S1 13: LW $63, 6(561) 14: ADD $81, 50, 51 I Which of the above instructions will have to be followed by a stall for the correct operation of the processor, given a 5 stage MIPS pipelined processor.
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- Processor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one cycle to complete, assuming zero wait state memory accesses. Processor C is a CISC processor with a 1.8 GHz clock rate. The average simple instruction requires one cycle to complete, assuming zero wait state memory accesses. The average complex instruction requires two cycles to complete, assuming zero wait state memory accesses. Processor R can’t directly implement the complex processing instructions of Processor C. Executing an equivalent set of simple instructions requires an average of three cycles to complete, assuming zero wait state memory accesses. Program S contains nothing but simple instructions. Program C executes 70% simple instructions and 30% complex instructions. Which processor will execute program S more quickly? Which processor will execute program C more quickly? At what percentage of complex instructions will the performance of the two processors be equal?A(n) ________________ instruction always alters the instruction execution sequence. A(n) ______________ instruction alters the instruction execution sequence only if a specified Condition is true.B. For the following 8085 assemble code, calculate the total execution time 0100: LXI 0103: MVI C,0 0105: NOP 0106: NOP 0107: DER C D,1000H 0108: JNZ 0105H 010A: MOV A,M 010B: OUT 05H SKIP : C. what is the single instruction equivalent to the following code: XOR DX,DX TEST AX,8000H JZ NOT Total execution time = SKIP DX
- 3. CPU x86/8088 executes the instruction ADD AX, CX; 2byte instruction, machine code is (03-C1). Before executing this instruction, CS=4200, IP = A000, AX = 7000, CX = 3000, (all data in hexadecimal). Describe this command, Draw a block diagram with signal and bus timing diagram to describe its operation for 8bit data bus system, Contents of CPU's registers before and after executing this instruction • What flag(s) will be affected after executing?b. Consider an ARM CPU that executes its instructions using a simple 3-stage pipeline consisting of fetch, decode and execute stages. Show how the instructions in the following ARM code would pass throught the pipeline by copying and completing the table below for the first nine cycles only. The first three lines have been completed for you. You should list if and where any structural hazards and/or any control hazards would occur. MOV R1, #42 LDRB R3, [RO, R1] EOR R3,R3, R2 STRB R3, [RO, R1] SUB R1,R1#1 crypt CMP R1, #0 BGE crypt MOV RO, #0 MOV PC, R14 Cycle Fetch Decode Execute 1 MOV R1,#42 2 LDRB R3, [RO, R1] MOV R1,#42 3 EOR R3,R3, R2 LDRB R3, [RO, R1] MOV R1,#42 4 6. 8Given a partial MIPS assembly code where only two instructions are explicitly given and the location where the first instruction is stored as specified, answer the questions that follow: Address Instruction Ox00000200 Loop: addi $t0, $Zero, -50 inst2 inst3 bne $s0, $t1, Loop Translate MIPS instructions bne $s0, $t1, Loop into machine code (give your answer in hex form 0XNNNNNNNN).
- If CS=2000H, DS=4000H, SS=6000H, ES=8000H, BX=1234H, BP=1234H, SP=5678H, SI=5678H, DI=9876H, IP=ABCDH; find the memory address for the following instructions: (i) MOV CX, [BP+SI+C3H] (ii) JNC 08H3 Consider the following MIPS assembly language instruction: nor $17, $12, $5 Register $12 contains [0096]16 and register $5 contains [0030] 16. What decimal will there be in register $17 after the instruction execut-Assume the usage of ARM assembly language instruction: STR R0,[R1],#0x8. Assume that Register R0 contains 0xA0, Register R1 contains 0x7008. Identify (i) contents of memory location 0x00A8 and (ii) R1 after executing the given instruction (i) 0xA0, (ii) 0x7008 (i) 0xA0, (ii) 0x7011 (i) 0xA2, (ii) 0x7008 (i) 0xA2, (ii) 0x7010
- Computer Science For the following instructions, explain the computation of the final memory address of a physical memory location of an operand. Also mention the corresponding addressing mode. The content of different registers and memory locations are as follows: Code Segment Register (CS)=2000h; IP=0405h; BX=0402h; DI=0303h; Data Segment Register (DS)=4000h; DL-65h; [1234h] =02h; [1235h]=03h; [1236h]-20h; [1237h]=40h; [1238] -20h; 1) MOV AL, [1235h] 2) ADD 0004[BX][DI], DL 3) MOV DH, [BX+DI] 4) JMP [2A] 5) JMP [1234h]Computer Science cs 218 assembly language Given the code fragment: lst dd 2, 3, 5, 7, 9 mov rsi, 4 mov eax, 1 mov rcx, 2 lp: add eax, dword [lst+rsi] add rsi, 4 loop lp mov ebx, dword [lst] What would be in the eax and ebx registers after execution (in hex)? eax ebx Must answer in hex (must precede number with 0x).Assume a pipelined CPU with data forwarding. In the following code, suppose the ADD instruction is in the EX stage. From which buffer register of the pipeline will the ADD instruction read the value of operand X1? LDUR X1, MEM[X2, #12] SUB X1, X2, X3 ADD X3, X4, X1 Question 6 options: EX/MEM МЕМ/WB ID/EX IF/ID