1) Implement a full adder with two 4 x 1 multiplexers. 2) Draw the logic diagram of a 2-to-4-line decoder using NOR gates only, include an enable input.
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- A d. B Figure 1 3. Referring to the logic circuit in Figure 1, determine: a. The simplified Boolean expression. b. The output waveform. C H c. Due to fabrication errors, lines d and f were shorted to the supply voltage. What happens to the output of the circuit? d. Your hardware resources are limited to 2-input NOR gate only. Draw the gate schematic of the simplified Boolean expression in 3(a).4) Draw a logic diagram of a divide-by-14 counter using IC 7493 and 2-input AND gate.4- Design the logic circuit of 4-to16 decoder using basic logic gates. Find its truth table and logic diagram. 5- What is the purpose of encoder circuit? 6- What is the purpose of decoder logic circuits?
- 1. A standard TTL gate performs what logic function for positive logic? 2. If all inputs of a TTL gate are binary 1, the output will be 3. The typical TTL logic levels are: Binary 0= 4. MOS combining both P- and N-channel in series is called 5. The CMOS logic levels are: binary 0 = volts and binary 1 = volts. volts and binary 1 = ______ volts.Design a " 2 to 4" Decoder with SEL' (active lo) 1. Generate the logic gates and the equations 2. Draw the timing waveforms for all inputs/SEL and output. 3. Create an application that could use this simple Decoder2. Design 6 lines to 64 lines Decoder using IC# 74138. You can use other logic gates/IC, if necessary.
- Q2. Implement full adder using 3 to 8 decoder and logic gates.Q4(a) Adder is divided into three types which are half adder, full adder, and parallel adder. Illustrate the implementation of full adder using half adder with necessary logic gates. (i) (ii) Figure Q4(a)(ii) shows the input timing diagram for a full adder. Illustrate the timing diagrams for output S and Cout- Cin Cout Figure Q4(a)(ii)Q4(a) Adder is divided into three types which are half adder, full adder, and parallel adder. Illustrate the implementation of full adder using half adder with necessary logic gates. (i) (ii) Figure Q4(a)(ii) shows the input timing diagram for a full adder. Illustrate the timing diagrams for output S and Cout- B Cin Cout Figure Q4(a)(ii) (iii) Given A = 111001 and B = 100010. Construct a 6-bit parallel adder to solve for A + B.
- d) Draw the schematics of 4-bit synchronous and asynchronous MOD-8 counters and comment on their pros and cons. e) Calculate the noise margin for a logic gate with the following logic levels: VIL = 1.1 V, VIH = 3.2 V, VOL = 0.6 V, VOH = 4.0 V.Figure 4 shows the decimal to BCD encoder logic. Assume that the 9 input and 3 inputare both HIGH.i) Determine the output code.ii) Is the value valid for BCD (8421) code?5) below is the accuracy table showing the output values for two separate binary number entries (W and Y) with a length of two bits. Get the simplest form of output functions with the Karnaugh diagram. Draw a logic diagram of the circuit that performs the function of these functions.Describe in detail which functions a, b and C perform for 2-bit binary numbers in the input.