It should be clear that disk striping can improve data transfer rate when the strip siz is small compared to the I/O request size. It should also be clear that RAID 0 pro vides improved performance relative to a single large disk, because multiple I/O re quests can be handled in parallel. However, in this latter case, is disk striping necessary? That is, does disk striping improve I/O request rate performance com- pared to a comparable disk array without striping?
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- Compare between the different Input-Output control techniques: programmed I/O, interrupt, DMA, and Channel IO. There are 3 major methods that can be used for allocating disk space; one is the contiguous allocation method. Search for one of the other 2 methods (Linked Allocation and Indexed Allocation) and compare its performance with the performance of contiguous allocation methods.It should be clear that disk striping can improve data transfer rate when the strip size is small compared to the I/O request size. It should also be clear that RAID 0 pro- vides improved performance relative to a single large disk, because multiple I/O re- quests can be handled in parallel. However, in this latter case, is disk striping necessary? That is, does disk striping improve I/O request rate performance com- pared to a comparable disk array without striping?For each of the below statements, indicate whether it is true or false. The primary purpose of RAID is for data backups. When reading data from a magnetic disk, the rotational latency increases linearly with the size of the request. In MIPS systems, one way to implement locks is with the MIPS test-and-set machine language instruction. Typically, data parallelism offers greater opportunities for achieving highly-parallel execution than does functional parallelism. In multiprocessors with a shared physical main memory, an access to a word of main memory always takes about the same amount of time no matter which word is being accessed and by which processor. SSD is faster to access than magnetic disk, but slower than DRAM main memory.
- Consider a disk that rotates at 3600 rpm. The seek time to move the head between ad- jacent tracks is 2 ms. There are 32 sectors per track, which are stored in linear order from sector 0 through sector 31. The head sees the sectors in ascending order. Assume the read/write head is positioned at the start of sector 1 on track 8. There is a main memory buffer large enough to hold an entire track. Data is transferred between disk locations by reading from the source track into the main memory buffer and then writing the date from the buffer to the target track. a. How long will it take to transfer sector 1 on track 8 to sector 1 on track 9? b. How long will it take to transfer all the sectors of track 8 to the corresponding sec- tors of track 9?In this problem, you will explore processor frequency in the context of the speed of light. Suppose you have overclocked a processor to 8,722.78MHz. This processor can execute one instruction per cycle. Further let us suppose that the system is accessing a magnetic disk (HD) with an access time of 11ms. 1. Determine the number of instructions the CPU must pause when waiting for a read request for data from the HD to complete. 2. Suppose that you are designing the machine architecture and want to guarantee the CPU can obtain data from memory within 4 CPU cycles. Given that the address has to travel from the CPU to the memory unit (MMU) and that the data has to travel from memory to the CPU, what is the maximum distance between CPU and the MMU if the signal on the memory bus propagates at 75% of the speed of light?Consider a disk with following specifications: 20 surface, 1000 tracks/surface, 16 sectors/track, data density 1 KB/sector, rotation speed 3000 rpm. The operating system initiates the transfer between the disk and the memory sector-wise. Once the head has been placed on the right track, the disk reads a sector in a single scan. It reads bits from the sector while the head is passing over the sector. The read bits are formed into bytes in a serial-in-parallel-out buffer and each byte is then transferred to memory. The disk writing is exactly a complementary process. For parts (c) and (d) below, assume memory read-write time = 0.1 microsecond/ byte, interrupt driven transfer has an interrupt overhead = 0.4 microseconds, the DMA initialization and termination overhead is negligible compared to the total sector transfer time. DMA requests are always granted. (a) What is the total capacity of the disk? (b) What is the data transfer rate? (c) What is the percentage of time the CPU is…
- Carefully read each sentence in this question. You may agree/disagree with each sentence (consider each sentence separately) if you have a good justification for doing so (not in more than 2 lines for each sentence). “A daisy chaining technique could result in starvation.” “The received data is saved in contiguous memory regions in DMA transfer.” “The most difficult method of device identification is multiple interrupt lines.” “An interrupt request takes longer for the CPU to handle than a DMA request.” “The architecture of InfiniBand operation is layered.”3. The advantage of I/O mapped devices to memory mapped is a. The former offers faster transfer of data b. The devices connected using I/O mapping have a bigger buffer space c. The devices have to deal with fewer address lines d. No advantage as suchPolling for an I/O completion can waste a large number of CPU cycles if the processor iterates a busy-waiting loop many times before the I/O completes. But if the I/O device is ready for service, polling can be much more efficient than is catching and dispatching an interrupt. Describe a hybrid strategy that combines polling, sleeping and interrupts for I/O service. For each of these strategies (pure polling, pure interrupts, hybrid) describe a computing environment in which that strategy is more efficient than is either of the others.
- Answer the following: A section of the memory space with the address from 0x6000 to 0x9FFF needs to be fully partitioned to two peripherals with the same memory size. The first peripheral's address starts at Ox6000 and ends at Ox . The second peripheral's address starts at Ox ends at Ox9FFF. and In embedded programming, let i = 13, then j =i<< 2; we have j = 0x wise operation, let i = 0x00ff and then i &= ~0x0010, we have i = Ox . And for bit-It is now possible to look at the benefits and drawbacks of shared and private L2 caches for single-, multi-, and multi-programmed workloads, and determine whether or not they ought to be re-evaluated now that on-chip L3 caches have been added to the chips. This is possible because on-chip L3 caches have been added to the chips.Difference between launching attack on 32-bit and 64-bit Program Using gdb to conduct an investigation on 64-bit programs is the same as that on 32-bit programs. The only difference is the name of the register for the frame pointer. In the x86 architecture, the frame pointer is ebp, while in the x64 architecture, it is rbp. Compared to buffer-overflow attacks on 32-bit machines, attacks on 64-bit machines is more difficult. The most difficult part is the address. Although the x64 architecture supports 64-bit address space, only the address from 0x00 through 0x00007FFFFFFFFFFF is allowed. That means for every address (8 bytes), the highest two bytes are always zeros. This causes a problem. In our buffer-overflow attacks, we need to store at least one address in the payload, and the payload in our lab will be copied into the stack via strcpy(). We know that the strcpy() function will stop copying when it sees a zero. Therefore, if zero appears in the middle of the payload, the content…